TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 203

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
BUSRQ (Internal)
DLEBCD
D1BSCP
D7 to D0
D3BFR
DLEBCD
D1BSCP
D2BLP
D7 to D0
D3BFR
D2BLP
1
Figure 3.14.3 Timing Diagram for SR Mode (Detail)
Figure 3.14.2 Timing Diagram for SR Mode
f
2
FP
= 78.02 Hz (at <FP8:0> = 120)
3
(240 seg = 30 byte)
of volume of 1com
Data transmission
1 picture (120 com)
t
SCP
N
display time
91C025-202
= 2 states
N+1
t
STOP
: Stop time
t
LP
: LP period
120
N+28
1
N+29
2
t
3
OPR
: CPU operating time
Note: XT = 1/32768 [s]
1 state = 1/f
120
TMP91C025
t
LPH
2007-02-28
SYS
= 0.5XT
1
[s]
2

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