TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 87

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(1) Master enable bits
(2) Data bus width selection
master bit which is used to enable or disable settings for the corresponding address
area. Writing 1 to this bit enables the settings. Reset disables (Sets to 0)<B0E>, <B1E>,
<B3E>, and enabled (sets to 1) <B2E>. This enables area CS2 only.
select/wait control register specifies the width of the data bus. This bit should be set to
0 when memory is to be accessed using a 16-bit data bus and to 1 when an 8-bit data
bus is to be used.
is known as dynamic bus sizing. For details of this bus operation see Table 3.6.2.
Bit 7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the
Bit 3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip
This process of changing the data bus width according to the address being accessed
91C025-85
TMP91C025
2007-02-28