TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 97

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Note: The same memory address is allocated to the timer register and the register buffer. When
(3) Timer registers (TA0REG and TA1REG)
<TA0RDE> = 0, the same value is written to the register buffer and the timer register; when
<TA0RDE> = 1, only the register buffer is written to.
in the timer register TA0REG or TA1REG matches the value in the corresponding up
counter, the comparator match detect signal goes active. If the value set in the timer
register is 00H, the signal goes active when the up counter overflows.
buffer.
buffer structure is enabled or disabled. It is disabled if <TA0RDE> = 0 and enabled if
<TA0RDE> = 1.
timer register when a 2
in PPG mode. Hence the double buffer cannot be used in timer mode.
buffer, write data to the timer register, set <TA0RDE> to 1, and write the following
data to the register buffer. Figure 3.7.3 show the configuration of TA0REG.
Timer registers 0 (TA0REG)
The address of each timer register is as follows.
All these registers are write only and cannot be read.
These are 8-bit registers which can be used to set a time interval. When the value set
The TA0REG are double buffer structure, each of which makes a pair with register
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double
When the double buffer is enabled, data is transferred from the register buffer to the
A reset initializes <TA0RDE> to 0, disabling the double buffer. To use the double
Register buffers 0
Internal data bus
TA0REG: 000102H
TA2REG: 00010AH
Shift trigger
Write
Figure 3.7.3 Configuration of TA0REG
n
overflow occurs in PWM mode, or at the start of the PPG cycle
91C025-95
TA01RUN<TA0RDE>
Y
Selector
TA1REG: 000103H
TA3REG: 00010BH
S
B
A
Matching detection in PPG cycle
2
Write to TA0REG
n
overflow of PWM
TMP91C025
2007-02-28