TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 129

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
3.9.2
X: Don’t care, −: Cannot be used
Select System
<SYSCK>
Operation of Each Circuit
(1) Prescaler
the prescaler outputs.
Clock
1 (fs)
0 (fc)
The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32 among
SYSCR<PRCK1:0> is divided by 4 and input to the prescaler as φT0. The prescaler can
be run by selecting the baud rate generator as the serial transfer clock.
There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using
Table 3.9.2 shows prescaler clock resolution into the baud rate generator.
Table 3.9.2 Prescaler Clock Resolution to Baud Rate Generator
Select Prescaler
10 (fc/16 clock)
<PRCK1:0>
00 (f
Clock
FPH
)
91C025-127
<GEAR2:0>
Gear Value
100 (fc/16)
001 (fc/2)
010 (fc/4)
011 (fc/8)
000 (fc)
XXX
XXX
Prescaler Output Clock Resolution
φT0
2
2
2
2
2
2
2
2
3
4
5
6
/fs
/fc
/fc
/fc
/fc
/fc
φT2
2
2
2
2
2
2
2
4
4
5
6
7
8
8
/fs
/fc
/fc
/fc
/fc
/fc
/fc
2
2
φT8
2
2
2
2
2
10
10
6
6
7
8
9
/fs
/fc
/fc
/fc
/fc
/fc
/fc
TMP91C025
φT32
2
2
2
2
2
2
2
2007-02-28
10
11
12
12
8
8
9
/fs
/fc
/fc
/fc
/fc
/fc
/fc

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