TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 173

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Analog Input Channel
(e) AD conversion time
(f) Storing and reading the results of AD conversion
Table 3.11.3 Correspondence between Analog Input Channels and
84 states (4.7 μs at f
channel.
The AD conversion data upper and lower registers (ADREG04H/L to
ADREG37H/L) store the AD conversion results. (ADREG04H/L to ADREG37H/L
are read-only registers.)
In channel fixed repeat conversion mode, the conversion results are stored
successively in registers ADREG04H/L to ADREG37H/L. In other modes, the AN0,
AN1, AN2 and AN3 conversion results are stored in ADREG04H/L, ADREG15H/L,
ADREG26H/L and ADREG37H/L respectively.
Table 3.11.3 shows the correspondence between the analog input channels and the
registers which are used to hold the results of AD conversion.
<ADRxRF>, bit0 of the AD conversion data lower register, is used as the AD
conversion data storage flag. The storage flag indicates whether the AD conversion
result register has been read or not. When a conversion result is stored in the AD
conversion result register, the flag is set to 1. When either of the AD conversion
result registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0.
Reading the AD conversion result also clears the AD conversion end flag
ADMOD0<EOCF> to 0.
(Port A)
AN0
AN1
AN2
AN3
AD Conversion Result Registers
Other than at Right
Conversion Modes
FPH
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
91C025-171
AD Conversion Result Register
= 36 MHz) are required for the AD conversion for one
Channel Fixed Repeat
Conversion Mode
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
(<ITM0>=1)
TMP91C025
2007-02-28