TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 48

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.4.3
Interrupt Controller Operation
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
flip-flop), an interrupt priority setting register and a micro DMA start vector register. The
interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to
0 in the following cases:
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•
•
•
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priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). 6 interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source. The priority of non-maskable interrupts
(Watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are
generated at the same time, the default priority (The interrupt with the lowest priority or,
in other words, the interrupt with the lowest vector value) is used to determine which
interrupt request is accepted first.
interrupt request flag and thus whether an interrupt request for a given channel has
occurred.
simulateous interrupts and its vector address to the CPU. The CPU compares the priority
value <IFF2:0> in the status register by the interrupt request signal with the priority value
set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than
the priority value by 1 (+1) in the CPU SR<IFF2:0>. Interrupt request where the priority
value equals or is higher than the set value are accepted simultaneously during the
previous interrupt routine.
CPU restores the priority value saved in the stack before the interrupt was generated to
the CPU SR<IFF2:0>.
vector. Writing the start vector of the interrupt source for the micro DMA processing (see
Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing.
The values must be set in the micro DMA parameter register (e.g. DMAS and DMAD) prior
to the micro DMA processing.
The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the
For each of the 36 interrupt channels there is an interrupt request flag (consisting of a
An interrupt priority can be set independently for each interrupt source by writing the
The 3rd and 7th bits of the interrupt priority setting register indicate the state of the
The interrupt controller sends the interrupt request with the highest priority among the
When interrupt processing is completed (after execution of the RETI instruction), the
The interrupt controller also has registers (4 channels) used to store the micro DMA start
When reset occurs
When the CPU reads the channel vector after accepted its interrupt
When executing an instruction that clears the interrupt
(Write DMA start vector to INTCLR register)
When the CPU receives a micro DMA request (When micro DMA is set)
When the micro DMA burst transfer is terminated
91C025-46
TMP91C025
2007-02-28