TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 202

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
3.14.4.2 Timer Out LCDCK
timer out (TA3OUT) outputs from internal TMRA23.
Example:
Reference: To maintain quality for display, please refer to following value for each gray
under a decimal point.
LCD source clock (LCDCK) can select low frequency (XT1, XT2: 32.768 [kHz]) or
The next equation calculates frame period.
Source clock for LCDC defines as XT [Hz] and then this t
Therefore if you set the frame period at 70 [Hz] under 120 COM,
XT should be above value.
In order to make XT = 29400 [Hz] under fc = 6 [MHz] with φT1 of timer3,
However T3 = (TA3REG) is 12.75 after calculate, it’s impossible to set the value
So if (TA3REG) is set 0CH, XT = 31250 [Hz]. And because of D = 3.5,
Frame period = 31250/(127 × 3.5)
Frame period = 1/(t
t
1/XT = T3 × 2 × 8/fc [s]
in short, XT = fc/(T3 × 2 × 8) [Hz]
Further if f
XT = 120 × 3.5 × 70
Frame period = 31250/(120 ×3.5)
LP
scale.
(You have to use settlement of frame frequency function, frame invert
adjustment function and timer out LCDCK.)
Monochrome: Frame period = 70 [Hz]
Here indicates the method that frame period is set 70 [Hz] by selecting
TA3OUT for source clock of LCD (fc = 6 [MHz], 120 COM).
= D/XT
= 29400 [Hz]
FP
= 74.404 [Hz]
is 127 (COM + 7) with correction,
= 70.30 ... [Hz]
91C025-201
LP
× f
FP
) [Hz]
T3: the value of timer resister (TA3REG)
t
D: The value is 3.5 at 120 COM
LP
: The period of D2BLP
LP
represents
TMP91C025
2007-02-28

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