TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 90

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(Setting example)
set to 16 bits and the number of waits is set to 0.
(4) Bus width and wait control for an area other than CS0 to CS3
(5) Selecting 16-Mbyte area/specified address area
(6) Procedure for setting chip select/wait control
In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is
MSAR0 = 01H
MAMR0 = 07H
B0CS = 83H
waits when memory locations which are not in one of the four user-specified address
areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for
areas other than CS0 to CS3.
designates the 16-Mbyte area 000FE0H to 000FFFH, 003000H to FFFFFFH as the
CS2 area. Setting B2CS<B2M> to 1 designates the address area specified by the start
address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if
B2CS<B2M> = 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are).
order:
•
•
•
The chip select/wait control register BEXCS controls the bus width and number of
Setting B2CS<B2M> (bit 6 of the chip select/wait control register for CS2) to 0
A reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area.
When using the chip select/wait control function, set the registers in the following
Set the memory start address registers MSAR0 to MSAR3.
Set the start addresses for CS0 to CS3.
Set the memory address mask registers MAMR0 to MAMR3.
Set the sizes of CS0 to CS3.
Set the chip select/wait control registers B0CS to B3CS.
Set the chip select output waveform, data bus width, number of waits and master
enable/disable status for
The CS0 to S3 pins can also function as pins P60 to P63. To output a chip select
signal using one of these pins, set the corresponding bit in the port 6 function
register P6FC to 1.
If a CS0 to S3 address is specified which is actually an internal I/O and RAM area
address, the CPU accesses the internal address area and no chip select signal is output on any
of the
CS
0
to
CS
Start address: 010000H
Address area: 64 Kbytes
ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings enabled.
3
pins.
91C025-88
CS
0
to
CS
3
.
TMP91C025
2007-02-28