TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 77

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.5.10
Port C (PC0 to PC5)
input or output. Resetting sets PC0 to PC5 to be an input ports. It also sets all bits of the
output latch register to 1.
as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing 1 to the
corresponding bit of the port C function register (PCFC).
ports .
(1) Port C0, C3 (TXD0/TXD1)
Port C0 to C5 are 6-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port pins, PC0 to PC5 can also function
Resetting resets all bits of the registers PCCR and PCFC to 0 and sets all pins to be input
channel TXD output pins. In case of use TXD0/TXD1, it is possible to logical invert by
setting the register PC<PC0, PC3>.
by the register PCODE<ODEPC0, ODEPC3>.
As well as functioning as I/O port pins, port C0 and C3 can also function as serial
And port C0 to C3 have a programmable open drain function which can be controlled
TXD0, TXD1
PC write
Output latch
S
Ditection control
Function control
(on bit basis)
(on bit basis)
PCFC write
PCCR write
PC Read
Figure 3.5.23 Port C0 and C3
Reset
Logical invert
91C025-75
A
B
Selector
Selector
S
S
B
A
PCODE<ODEPC0, C3>
set possible
Open-drain
PC0 (TXD0)
PC3 (TXD1)
TMP91C025
2007-02-28