TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 110

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

TA0REG-WR
TA01RUN<TA0RDE>
TA01MOD<TA0CLK1:0>
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
<TA1RUN> should be set to 1, so that UC1 is set for counting.
will be shifted into TA0REG each time TA1REG matches UC0.
varied).
TA0IN
φT1
φT4
φT16
In this mode, a programmable square wave is generated by inverting the timer
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN
Figure 3.7.14 shows a block diagram representing this mode.
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
Use of the double buffer facilitates the handling of low-duty waves (when duty is
Selector
(Value to be compared)
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
Match with TA1REG
Selector
Shift trigger
Register buffer
Figure 3.7.15 Operation of Register Buffer
Register buffer
Match with
Comparator
TA0REG
TA0REG
TA0REG
up counter (UC 0)
Internal data bus
8-bit
91C025-108
(Up counter = Q
Comparator
TA1REG
Q
TA01RUN<TA0RUN>
1
1
)
Q
2
(Up countner = Q
TA1OUT
TA1FF
Inversion
Shift from register buffer
TA1FFCR<TA1FFIE>
INTTA0
INTTA1
2
)
Q
2
TA0REG (Register buffer)
write
Q
3
TMP91C025
2007-02-28