TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 142

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
BR0ADD
(0204H)
(0203H)
BR0CR
0
1
+(16 − K)/16 division enable
Bit symbol
Read/Write
After reset
Function
BR0ADD
<BR0K3:0>
Bit symbol
Read/Write
After reset
Function
Disable
Enable
1111 (K = 15)
0001 (K = 1)
Note1:Availability of +(16-K)/16 division function
Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division
0000
to
Figure 3.9.11 Baud Rate Generator Control (SIO0, BR0CR, BR0ADD)
BR0CR
<BR0S3:0>
function is used. Writes to unused bits in the BR0ADD register do not affext operation, and undefined data is
read from these unused bits.
Always
write 0.
Sets baud rate generator frequency divisor
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in
I/O interface mode.
N
2 to 15
1 , 16
7
0
7
+(16 − K)/16
division.
0000 (N = 16)
0001 (N = 1)
0: Disable
1: Enable
BR0ADDE
BR0CR<BR0ADDE> = 1
Disable
Disable
6
or
0
6
UART mode
×
00: φT0
01: φT2
10: φT8
11: φT32
N + (16 − K)/16
Setting the input clock of baud rate generator
1111 (N = 15)
BR0CK1
0010 (N = 2)
00
01
10
11
Divided by
5
5
0
Disable
91C025-140
to
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
BR0CK0
I/O mode
4
4
0
×
×
BR0CR<BR0ADDE> = 0
0001 (N = 1) (UART only)
R/W
1111 (N = 15)
0000 (N = 16)
Divided by N
BR0K3
BR0S3
to
0
3
3
0
Setting the divided frequency “N”.
(Divided by N + (16 − K)/16)
Sets frequency divisor “K”.
BR0S2
BR0K2
2
0
2
0
(0 to F)
R/W
BR0S1
BR0K1
1
1
0
0
BR0S0
BR0K0
TMP91C025
0
0
0
0
2007-02-28

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