TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 177

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.12.3
Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please
Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once.
Control Registers
(1) Watchdog timer mode register (WDMOD)
(2) Watchdog timer control register (WDCR)
The watchdog timer WDT is controlled by two control registers WDMOD and WDCR.
a.
b.
c.
refer to setting example.)
0 and then writing the disable code (B1H) to the WDCR register.
•
•
This register is used to disable and clear the binary counter for the watchdog timer.
Disable control the watchdog timer can be disabled by clearing WDMOD<WDTE> to
when
WDMOD<WDTP1:0> = 00.
To disable the watchdog timer, it is necessary to set this bit to 0 and to write the
disable code (B1H) to the watchdog timer control register WDCR. This makes it
difficult for the watchdog timer to be disabled by runaway.
the enabled state merely by setting <WDTE> to 1.
RESET terminal internally. Since WDMOD<RESCR>is initialized to 0 on reset, a
reset by the watchdog timer will not be performed.
(4EH) to the WDCR register.
Enable control
Watchdog timer clear control
Setting the detection time for the watchdog timer in <WDTP1:0>
Watchdog timer enable/disable control register <WDTE>
Watchdog timer out reset connection <RESCR>
WDCR
WDCR
WDMOD
WDCR
This 2-bit register is used for setting the watchdog timer interrupt time used
The detection times for WDT are shown in Figure 3.12.4.
After reset, WDMOD<WDTE> is initialized to 1, enabling the watchdog timer.
However, it is possible to return the watchdog timer from the disabled state to
This register is used to connect the output of the watchdog timer with the
Set WDMOD<WDTE> to 1.
To clear the binary counter and cause counting to resume, write the clear code
detecting
← 0 1 0 0 1 1 1 0
← 0 1 0 0 1 1 1 0
← 0 − − X X − − 0
← 1 0 1 1 0 0 0 1
runaway.
91C025-175
After
Write the clear code (4EH).
Write the clear code (4EH).
Clear WDMOD<WDTE> to 0.
Write the disable code (B1H).
reset,
this
register
is
initialized
TMP91C025
2007-02-28
to