TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 200

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.14.4
Shift-register Type LCD Driver Control Mode (SR type)
control registers before setting start register.
source memory.
data bus.
waveform synchronizes with data transmission.
re-start.
3.14.2, Figure 3.14.3.
and CPU stop time/stop ratio are shown in Table 3.14.4. And, f
common number is shown in Table 3.14.5.
Figure 3.14.5.
Set the mode of operation, start address of source data save memory and LCD size to
After set start register LCDC outputs bus release request to CPU and read data from
After that LCDC transmits data of volume of LCD size to external LCD driver through
At this time, control signals (D1BSCP etc.) connected LCD driver output specified
After finish data transmission, LCDC cancels the bus release request and CPU will
LCDC timing figure in the case of 240 seg × 120 com and BYTE mode is shown in Figure
The table of t
Moreover, the example of a 240 seg × 120 com LCD driver connection circuit is shown in
LP
(D2BLP pin cycle) by the number of segments and the common number
91C025-199
FP
(Frame frequency) by the
TMP91C025
2007-02-28