TMP91xy25FG Toshiba, TMP91xy25FG Datasheet
TMP91xy25FG
Specifications of TMP91xy25FG
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TMP91xy25FG Summary of contents
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... TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C025FG Semiconductor Company ...
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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (INT0 ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties ...
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Built-in RAM: None Built-in ROM: None (4) External memory expansion • Expandable up to 104 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus ... Dynamic data bus sizing • Separate bus system (5) 8-bit ...
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... Operating voltage • 3 3.6 V (fc max = 36 MHz) CC • 2 3.6 V (fc max = 27 MHz) CC • 3.6 V (fc max = 16 MHz (22) Package • 100-pin QFP: P-LQFP100-1414-0.50F, chip form supply also available. For details, contact your local Toshiba sales representative. 91C025-3 TMP91C025 2007-02-28 ...
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AN2/MX (P82) AN3/MY/ (P83) ADTRG 10-bit 4-channel AN0, AN1 (P80, P81) AD converter AVCC, AVSS VREFH, VREFL TXD0 (PC0) SIO/UART/IrDA RXD0 (PC1) (SIO0) SCLK0/ (PC2) CTS 0 TXD1 (PC3) SIO/UART RXD1 (PC4) (SIO1) SCLK1/ CTS (PC5) 1 PX/INT2 (PB5) Touch ...
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Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C025, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C025FG. VREFL 1 AVSS AVCC P80/AN0 P81/AN1 ...
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PAD Layout (Chip size 4.58 mm × 4.63 mm) Pin X Y Name No. Point Point −2151 1 VREFL 1627 −2151 2 AVSS 1502 −2151 3 AVCC 1376 −2151 4 P80 1251 −2151 5 P81 1126 −2151 6 P82 ...
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Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.3.1 Pin Names and Functions (1/3) Number Pin Name I/O of Pins I/O P10 to P17 8 I/O ...
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Table 2.3.2 Pin Names and Functions (2/3) Number Pin Name I/O of Pins P80 to P81 2 Input AN0 to AN1 Input P82 1 Input AN2 Input MX Input P83 1 Input AN3 Input ADTRG Input MY Input P90 to ...
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Table 2.3.3 Pin Names and Functions. (3/3) Number Pin Name I/O of Pins PC2 1 I/O SCLK0 I/O CTS 0 Input PC3 1 I/O TXD1 Output PC4 1 I/O RXD1 Input PC5 1 I/O SCLK1 I/O CTS 1 Input XT1 ...
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Operation This following describes block by block the functions and operation of the TMP91C025. Notes and restrictions for eatch book are outlined in 6, precautions and restrictions at the end of this manual. 3.1 CPU The TMP91C025 incorporates a ...
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Read Figure 3.1.1 Reset Timing Chart 91C025-11 TMP91C025 Write 2007-02-28 ...
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Memory Map Figure 3.2 memory map of the TMP91C025. 000000H 000100H 000FE0H 001000H 010000H External memory FFFF00H Vector table (256 bytes) FFFFFFH Note: Address 000FE0H to 000FEFH is assigned for the external memory area of built-in RAM ...
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Triple Clock Function and Standby Function TMP91C025 contains noise-reduction circuit used for low-power and low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 System Clock Controller 3.3.4 Prescaler Clock ...
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The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (the X1, X2, XT1 and XT2 pins and DFM). Figure ...
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Block Diagram of System Clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> DFMCR0<ACT1:0, DLUPTM> Warm-up timer (High/low frequency oscillator), Lock up timer (DFM) SYSCR0 <XTEN, RXTEN> XT1 Low-frequency fs oscillator XT2 f DFM SYSCR0 <XEN, RXEN> Clock Doubler (DFM) X1 High-frequency oscillator X2 f ...
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SFRs 7 SYSCR0 Bit symbol XEN (00E0H) Read/Write After reset 1 Function High- Low- frequency frequency oscillator (fc) oscillator (fs) 0: Stop 0: Stop 1: Oscillation 1: Oscillation 7 SYSCR1 Bit symbol (00E1H) Read/Write After reset Function 7 SYSCR2 ...
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Symbol Name Address 7 ACT1 R/W 0 DFM DFM LUP select f DFMCR0 control E8H 00 STOP register 0 01 RUN 10 RUN 11 RUN D7 R/W DFM DFMCR1 0 control E9H register 1 Limitation point on the use of ...
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EMCCR0 Bit symbol PROTECT TA3LCDE (00E3H) Read/Write R After reset 0 Function Protect flag LCDC source 0: Off CLK kHz 1: TA3OUT EMCCR1 Bit symbol (00E4H) Read/Write After reset Switching the protect ON/OFF by write ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc ...
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Setting the clock) Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H LD (SYSCR2), - X11 - - - - B SET 6, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) ...
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Setting the clock) Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H LD (SYSCR2), -X10 - - - - B SET 7, (SYSCR0) SET 2, (SYSCR0) WUP: BIT 2, (SYSCR0) JR ...
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Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> set according to the contents of the clock gear select register SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the ...
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Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1) there is a prescaler which can divide the clock. The φT0 clock input to the prescaler is either the clock f divided by 4. The setting ...
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Limitation point on the use of DFM 1. It’s prohibited to execute DFM enable/disable control in the SLOW mode (fs) (write to DFMCR0<ACT1:0> = “10”). You should control DFM in the NORMAL mode you stop DFM operation during ...
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Change/stop control (OK) DFM use mode (f ) → High-frequency oscillator operation mode (f DFM stop → Low-frequency oscillator operation mode (fs) → High-frequency oscillator stop LD (DFMCR0 (DFMCR0), 00 ...
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Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents ...
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Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin C1 Resonator C2 XT2 pin (Setting method) The drivability of EMCCR0<DRVOSCL> register. By reset, <DRVOSCL> is initialized to ...
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Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that the state which is fetch ...
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Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When write operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. ...
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Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: ...
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How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. ...
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Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode INTWDT INT0 to INT3 (Note 1) INTALM0 to INTALM4 INTTA0 to INTTA3 INTRX0 to INTRX1, TX0 to TX1 INTAD INTKEY INTRTC INTLCD RESET ...
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Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of ...
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STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<DRVE> register. Table 3.3.6, Table 3.3.7 summarizes the state of these pins in ...
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The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to INTx. Address SYSCR0 EQU SYSCR1 EQU SYSCR2 EQU 8FFDH LD 9000H LD 9002H LD 9005H HALT INTx 9006H Note: When different modes ...
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When the CPU is Input Port Name Function During When Name Reset Used as function Pin – D0-7 ON upon OFF external P10-17 D8-15 read P56 (*1) WAIT ON ON – P80-82 (*2) OFF ADTRG P83 (*2) P90 (*1) KI0 ...
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Port Output Function During Name Name Reset Used as function – D0-7 ON upon OFF external P10-17 D8-15 – A0-15 ON P20-27 A16-23 – P56 (*1) OFF CS 0 P60 CS 1 P61 , P62 ...
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Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C025 has a total of 37 interrupts divided into the following three types: • Interrupts generated by CPU: 9 sources (Software ...
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Interrupt processing Interrupt specified by micro DMA start vector? No Interrupt vector value V read Interrupt request F/F clear General-purpose interrupt PUSH PC processing PUSH SR SR<IFF2:0> ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 PC ...
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General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the ...
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Table 3.4.1 TMP91C025 Interrupt Vectors Table Default Type Priority Source of Micro DMA Request 1 Reset or “SWI 0” instruction 2 “SWI 1” instruction 3 INTUNDEF: illegal instruction or “SWI 2” instruction 4 “SWI 3” instruction Non- 5 “SWI 4” ...
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Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C025 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the ...
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If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel ...
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Soft start function In addition to starting the micro DMA function by interrupts, TMP91C025 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to ...
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Detailed description of the transfer mode register 8 bits DMAM0 Mode DMAM3 Number of Transfer Bytes 000 000 00 Byte transfer (fixed) 01 Word transfer 10 4-bit transfer 001 00 Byte transfer 01 Word transfer ...
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Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. ...
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Figure 3.4.3 Block Diagram of Interrupt Controller 91C025-47 TMP91C025 2007-02-28 ...
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Interrupt level setting registers Symbol Name Address INT0 and IADC INTAD 90H INTE0AD enable INT1 and I2C INT2 91H INTE12 enable INT3 and IA4C INTALM4 92H INTE3ALM4 enable INTALM0 and IA1C 93H INTEALM01 INTALM1 enable INTALM2 and IA3C 94H ...
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Symbol Name Address 7 Interrupt ITX0C INTES0 enable 98H R serial 0 0 INTRX1 & ITXT1C INTES1 99H INTTX1 R enable 0 ILCD1C INTLCD INTELCD 9AH enable R 0 INTTC0 & ITC1C INTETC01 9BH INTTC1 R enable 0 INTTC2 & ...
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External interrupt control Symbol Name Address 7 − Interrupt 8CH input 0 IIMC mode Always (Prohibit control write 0. RMW) INT0 level enable 0 edge detect INT 1 High level INT (3) Interrupt request flag clear register The interrupt ...
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Symbol Name Address DMA0 DMA0V start 80H vector DMA1 DMA1V start 81H vector DMA2 DMA2V start 82H vector DMA3 DMA3V start 83H vector (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the ...
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Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may ...
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Port Functions The TMP91C025 features 38-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 ...
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Table 3.5.2 I/O Registers and Specifications (1/2) Port Pin Name Port 1 P10 to P17 Input port (Note 1) Output port D8 to D15 bus Port 2 P20 to P27 Output port A16 to A23 output Port 5 P56 input ...
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Table 3.5.3 I/O Registers and Specifications (2/2) Port Pin Name Port C PC0 to PC5 Input port Output port PC0 TXD0 output PC1 RXD0 input PC2 SCLK0 input SCLK0 output input CTS 0 PC3 TXD1 output PC4 RXD1 input PC5 ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting , the control register P1CR to 0 and sets port ...
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Port 2 (P20 to P27) Port 8-bit output port. In addition to functioning as a output port, port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for ...
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P0 P1 Bit symbol P17 (0000H) (0001H) Read/Write After reset 7 P1CR Bit symbol P17C (0004H) Read/Write After reset 0/1 (Note2) Function 7 P2 Bit symbol P27 (0006H) Read/Write After reset 1 7 P2FC Bit symbol P27F (0009H) Read/Write ...
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Port Z (PZ2 to PZ3) Port 2-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting sets all bits of the output latch addition to functioning as a ...
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Reset Direction control (on bit basis) PZCR write Function conrtol (on bit basis) PZFC write Output latch B Output buffer C PZ write R/W SRWR PZ read Figure 3.5.5 Port Z3 91C025-60 TMP91C025 P-ch (Programmable pull up) ...
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Bit symbol PZ Read/Write (007DH) After reset Function 7 Bit symbol PZCR Read/Write (007EH) After reset Function 7 Bit symbol PZFC (007FH) Read/Write After reset Function Note 1: Output latch register is set to 1. Note 2: Read-modify-write is ...
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Port 5 (P56) Port 1-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting sets all bits of the output latch addition to functioning as a general-purpose I/O ...
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P5 Bit symbol (000DH) Read/Write Data from After reset external port (Output latch register is set to 0(Output latch Function register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON 7 P5CR Bit symbol (0010H) Read/Write After ...
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Port 6 (P60 to P65) Port are 6-bit output ports. Resetting sets output latch of P62 to “0” and output latches of P60 to P61, P63 to P65 to 1. Port6 also function as chip-select output ...
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Bit symbol P6 (0012H) Read/Write After reset 7 P6FC Bit symbol (0015H) Read/Write After reset Function 7 P6FC2 Bit symbol (001BH) Read/Write After reset Function , , EA25 setting SRUB <P65F> 0 <P65F2> 0 P65 SRUB ...
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Port 8 (P80 to P83) Port 4-bit input port and can also be used as the analog input pins for the internal AD converter. P83 can also be used as ADTRG pin for the AD converter. ...
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Port 9 (P90 to P97) Port are 8-bit input ports with pull-up resistors. In addition to functioning as general-purpose I/O port, port can also Key-on wakeup function as Key board interface. The various ...
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Port A (PA0 to PA3) Port A0 to PA3 are 4-bit output ports, and also used Key board interface pin KO0 to KO3 which can set open drain output buffer. Writing 1 to the corresponding bit of the port ...
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Reset Function control PAFC2 write Output buffer set PAFC write S Output latch PA write PA read TA1OUT TA3OUT Figure 3.5.16 Port A1, 2 Reset Function control PAFC2 write Output buffer set PAFC write S Output latch PA write PA ...
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PA Bit symbol (001EH) Read/Write After reset 7 PAFC Bit symbol (0021H) Read/Write After reset Function 7 PAFC2 Bit symbol (0020H) Read/Write After reset Function Note: Read-modify-write is prohibited for PAFC and PAFC2. Port A register ...
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Port B (PB3 to PB6) Port B3 to PB6 is a 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port input port. In addition to functioning as ...
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PB4 (INT1) Reset Direction control (on bits basis) PBCR write Function control (on bits basis) PBFC write S Output latch PB write PB read INT1 TA0IN Figure 3.5.20 Port Selector A Rising/falling edge detection IIMC<I1EDGE > ...
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PB5 (INT2), PB6(INT3) Function control (on bits basis) INT2 . INT3 Reset TSICR0<PXEN> <PYEN> PBFC write TSICR0<TSI7> PB read TSICR1<DBC7> Rising/falling Selector edge detection B IIMC<I2EDGE, I3EDGE > TSICR0<TWIEN, TSI7> TSICR0<PXEN> TSICR<TSI7> Figure 3.5.21 Port B5, B6 ...
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PB Bit symbol (0022H) Read/Write After reset 7 PBCR Bit symbol (0024H) Read/Write After reset Function 7 PBFC Bit symbol PB6F (0025H) Read/Write After reset Function 0: Port 1: INT3 Note 1: Output latch register is set to 1. ...
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Port C (PC0 to PC5) Port are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 input ports. It also sets all bits ...
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Port C1, C4 (RXD0, RXD1) Port C1 and C4 are I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD0/RXD1 possible to logical invert by setting the ...
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PC Bit symbol (0023H) Read/Write After reset 7 PCCR Bit symbol (0026H) Read/Write After reset Function 7 PCFC Bit symbol (0027H) Read/Write After reset Function 7 PCODE Bit symbol (0028H) Read/Write After reset Function Note 1: Read-modify-write is prohibited ...
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Port D (PD0 to PD4, PD7) Port 6-bit output port. Resetting sets the output latch PD to “1”, and PD0 to PD4, PD7 pin output “1”. In addition to functioning as output port, port D also ...
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Chip Select/Wait Controller On the TM91C025, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The ...
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Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper 8 bits (A23 to A16) of ...
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Memory address mask registers Figure 3.6.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of ...
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Setting memory start addresses and address areas Figure 3.6.4 show an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0<S23:16> (Corresponding to the upper 8-bits of ...
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Address area size specification Table 3.6.1 shows the relationship between CS area and area size. Triangle (Δ) indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using ...
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B0CS Bit symbol B0E (00C0H) Read/Write W After reset 0 Function 0: Disable 1: Enable B1CS Bit symbol B1E (00C1H) Read/Write W After reset 0 Function 0: Disable 1: Enable B2CS Bit symbol B2E (00C2H) Read/Write After reset 1 ...
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Master enable bits Bit 7 (<B0E>, <B1E>, <B2E> or <B3E> chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables ...
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Indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes too high-impedance; also, that the write strobe signal for the bus remains inactive. Table 3.6.2 ...
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Wait control Bits (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2> chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait ...
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Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified ...
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Connecting External Memory Figure 3.6.7 shows an example of how to connect external memory to the TMP91C025. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C025 ...
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TMP91C025 RD SRLB SRUB SRWR [15:0] Not connect Figure 3.6.8 How to Connect to 16-Bit SRAM for TMP91C025 91C025-90 TMP91C025 16-bit SRAM OE LDS UDS I/O [16: ...
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Timers (TMRA) The TMP91C025 features 4 channel (TMRA0 to TMRA3) built-in 8-bit timers. These timers are paired into 2 modules: TMRA01 and TMRA23. Each module consists of 2 channels and can operate in any of the following 4 ...
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Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 91C025-92 TMP91C025 2007-02-28 ...
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Figure 3.7.2 TMRA23 Block Diagram 91C025-93 TMP91C025 2007-02-28 ...
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Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The φT0 as the input clock to prescaler is a clock divided by 4 which selected using the prescaler clock selection register SYSCR0<PRCK1:0>. The ...
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Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator ...
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Comparator (CP0) The comparator compares the value counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If ...
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SFRs 7 TA01RUN Bit symbol TA0RDE (0100H) Read/Write R/W After reset 0 Function Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 Disable 1 Enable Note: The values of bits TA01RUN are undefined ...
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TA01MOD (0104H) Bit symbol TA01M1 TA01M0 Read/Write After reset 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA01 Mode Register PWM01 PWM00 TA1CLK1 ...
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TA23MOD Bit Symbol TA23M1 (010CH) Read/Write After reset 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA23 Mode Register TA23M0 PWM21 PWM20 TA3CLK1 R/W ...
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TA1FFCR Bit symbol (0105H) Read/Write After reset Function Read-modify -write instructions are prohibited. TMRA1 Flip-Flop Control Register TA1FFC1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care Figure 3.7.7 TMRA Registers ...
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TA3FFCR Bit symbol (010DH) Read/Write After reset Function Read-modify -write instructions are prohibited. TMRA3 Flip-Flop Control Register TA3FFC1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care Figure 3.7.8 TMRA Registers ...
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TA0REG bit Symbol (0102H) Read/Write After reset TA1REG bit Symbol (0103H) Read/Write After reset TA2REG bit Symbol (010AH) Read/Write After reset TA3REG bit Symbol (010BH) Read/Write After reset Note: The above registers are prohibited read-modify-write instruction. TMRA register 6 ...
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Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Setting its function or counter data for TMRA0 and TMRA1 after stop these registers. a. Generating interrupts at a ...
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Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.2-μs square wave pulse from ...
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Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up counter 1 2 ...
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A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD<TA01M1:0> to 01. In 16-bit timer ...
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PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 ...
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In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be ...
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To generate 1/4-duty 50 kHz pulses ( MHz): 20 μs ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: f Calculate the value which should be set in the timer register. To ...
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PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output ...
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In this mode, the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match ...
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Select System Select Prescaler Gear Value Clock Clock SYSCR1 SYSCR1 SYSCR0 <GEAR2:0> <SYSCK> <PRCK1:0> 1 (fs) XXX 000 (fc) 001 (fc/ FPH 010 (fc/4) 0 (fc) 011 (fc/8) 100 (fc/16) XXX 10 (fc/16 clock) XXX: Don’t care ...
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LCDC and MELODY/ALARM circuit supply mode This function can operate only TMRA3. It can use LCDC and MELODY/ALARM source clock TA3 clock generated by TMRA3. But this function is special mode, without low clock (XTIN, XTOUT) so keep the ...
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External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 104 Mbytes by having 4 local areas. Address pins to external memory are 2 extended address bus pins (EA24, EA25 extended chip ...
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Recommendable Memory Map The recommendation logic address memory map at the time of varieties extension memory correspondence is shown in Figure 3.8.1. And a physical-address map is shown in Figure 3.8.2. However, when memory area is less than 16 ...
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LOCAL0 CS 3 for data RAM (8 Mbytes) 000000H BANK0 BANK1 BANK2 BANK3 BANK4 Internal-I/O BANK5 BANK6 BANK7 800000H 1000000H : Internal area : Overlapped with COMMON area Figure 3.8.2 Physical Address Map LOCAL1 LOCAL2 ...
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Control Registers Set a bank setting value and bank enable/disable in each local register in the common area. At this time, also specify the pin function and mapping by the CS/WAIT controller. When the CPU outputs the logical address ...
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Data Address TMP91C025 , ( , : SRAM HWR CS 2 EA24, EA25 CS 3 *In case of 16-bit bus memory TMP91C025 Control signals D [0:15 A16 Figure 3.8.4 ...
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Setting ;CS0 LD (MSAR0), 00H LD (MAMR0), FFH LD (B0CS), 89H ;CS1 LD (MSAR1), 40H LD (MAMR1), FFH LD (B1CS), 80H ;CS2 LD (MSAR2), C0H LD (MAMR2), 7FH LD (B2CS), C3H ;CS3 LD (MSAR3), 80H LD (MAMR3), 7FH LD ...
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Operation ;***** /CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG a00000H ORG c00000H ORG E00000H LD (LOCAL3), 85H LDW HL,(800000H) LD (LOCAL3), 88H LDW BC,(800000H) to ORG FFFFFFH ;***** /CS3 ***** ORG 0000000H ORG ...
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Operation ;***** /CS2 ***** ORG 000000H ORG 200000H NOP to JP E00100H ORG 400000H ORG 600000H NOP to JP E00200H ORG 800000H ORG a00000H ORG c00000H !!!! Program Start !!!! ORG E00000H LD (LOCAL2), 81H JP C00000H to ORG ...
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At bank operation S/W Example 3 of the above, Figure 3.8.7 shows example of program jump. In the same way with before example, two dot line squares show each ROM and ’s option ROM. Program start from E00000H common address, ...
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Serial Channels TMP91C025 includes 2 serial I/O channels. For both channels either UART mode (Asynchronous transmission) or I/O Interface mode (Synchronous transmission) can be selected. • I/O interface mode • UART mode In mode 1 and mode 2 a ...
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Mode 0 (I/O interface mode) Bit0 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 Parity Start Bit0 1 2 • Mode 2 (8-bit UART mode) No parity Start Bit0 1 ...
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Block Diagrams Figure 3.9 block diagram representing serial channel 0. Prescaler φ φT2 φT8 φT32 Serial clock generation circuit BR0CR <BR0CK1:0> BR0CR <BR0S3:0> φ T0 φ T2 φ T8 φ T32 ...
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Prescaler φ φT2 φT8 φT32 Serial clock generation circuit BR1CR <BR1CK1:0> BR1CR <BR1S3:0> φ T0 φ T2 φ T8 φ T32 BR1CR <BR1ADDE> Baud rate generator f SYS SCLK1 Concurrent with PC5 I/O interface ...
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Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR<PRCK1:0> is divided by 4 and input to the prescaler as φT0. The prescaler can be run by ...
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Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is ...
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Integer divider (N divider) For example, when the source clock frequency (fc) = 12.288 MHz, the input clock frequency = φT2 (fc/16), the frequency divider N (BR0CR<BR0S3:0> and BR0CR<BR0ADDE> the baud rate in UART mode ...
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Table 3.9.3 Transfer Rate Selection (when baud rate generator is used and BR0CR<BR0ADDE> [MHz] Frequency Divider N (BR0CR<BR0S3:0>) 9.830400 ↑ ↑ ↑ 12.288000 ↑ 14.745600 ↑ ↑ ↑ 19.6608 ↑ ↑ ↑ ↑ 22.1184 24.576 ↑ ↑ ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> the basic clock is generated by dividing the output ...
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The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When bits ...
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Handshake function Use of pin allows data can be sent in units of one frame; thus, Overrun CTS errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD<CTSE> setting. When the CTS transmission is halted until ...
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Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates ...
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Timing generation a. In UART mode Receiving Mode 9 Bits Center of last bit. Interrupt Timing (Bit8) Framing Error Timing Center of stop bit. Parity Error Timing Center of last bit. Overrun Error Timing (Bit8) Note: In 9-Bit and ...
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SFRs 7 SC0MOD0 Bit symbol TB8 (0202H) Read/Write After reset 0 Function Transfer Hand shake data bit8. 0: CTS 1: CTS Figure 3.9.7 Serial Mode Control Register (SIO0, SC0MOD0 CTSE RXE WU SM1 R ...
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Bit symbol TB8 SC1MOD0 (020AH) Read/Write After reset 0 Function Transfer data bit8. Figure 3.9.8 Serial Mode Control Register (SIO1, SC1MOD0 CTSE RXE WU R Hand shake Receive Wakeup Serial transmission 0: CTS ...
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Bit symbol RB8 EVEN SC0CR (0201H) Read/Write R After reset Undefined Function Received Parity data bit8. 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with a bit ...
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Bit symbol RB8 EVEN SC1CR Read/Write R (0209H) After reset Undefined Function Received Parity data bit8. 0: Odd 1: Even Note: As all error flags are cleared after reading do not test only a single bit with a bit ...
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Bit symbol BR0ADDE BR0CR (0203H) Read/Write After reset 0 +(16 − K)/16 Function Always write 0. division. 0: Disable 1: Enable +(16 − K)/16 division enable 0 Disable 1 Enable 7 BR0ADD Bit symbol (0204H) Read/Write After reset ...
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Bit symbol BR1ADDE BR1CR (020BH) Read/Write After reset 0 +(16 − K)/16 Function Always write 0. division. 0: Disable 1: Enable +(16 − K)/16 division enable 0 Disabled 1 Enabled 7 BR1ADD Bit symbol (020CH) Read/Write After reset ...
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TB7 TB6 SC0BUF (0200H RB7 RB6 Note: Prohibit read-modify-write for SC0BUF. Figure 3.9.13 Serial Transmission/Receiving Buffer Registers (SIO0, SC0BUF) 7 SC0MOD1 Bit symbol I2S0 (0205H) Read/Write R/W After reset 0 Function IDLE2 0: Stop 1: Run ...
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Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK ...
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Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all data is output, INTES0<ITX0C> will be ...
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Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit ...
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Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to 0 and set enable the interrupt level ( the transfer interrupt. In the transfer interrupt program, ...
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Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting serial channel mode register SC0MOD0 <SM1:0> to 01. In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by ...
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Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: f FPH Main settings ← − − − − − − 0 − PCCR SC0MOD ← − ...
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Protocol a. Select 9-bit UART mode on the master and slave controllers. b. Set the SC0MOD0<WU> bit on each slave controller enable data receiving. c. The master controller transmits one-frame data including the 8-bit select code for ...
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To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. SYS TXD RXD Master Figure 3.9.24 UART Block Connection Since serial channels 0 and 1 operate in exactly the ...
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Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.25 shows the block diagram. Transmisison data SIO0 Receive data TMP91C025 Figure 3.9.25 IrDA Block Diagram (1) Modulation of the transmission data When the ...
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Data format The data format is fixed as follows: • Data length: 8 bits • Parity bits: None • Stop bits: 1 Any other settings don’t guarantee the normal operation. (4) SFR Figure 3.9.28 shows the control register SIRCR. ...
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As the same reason, + (16 − K)/16 division functions in the baud rate generator of SIO0 can not be used to generate 115.2 kbps baud-rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 divisions ...
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SIRCR Bit symbol PLSEL RXSEL (0207H) Read/Write After reset 0 Function Select Receive transmit data. pulse 0: H pulse width pulse 0: 3/ TXEN RXEN SIRWD3 R ...
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Touch Screen Interface (TSI) The TMP91C025 has an interface for 4-terminal resistor network touch-screen. This interface supports two procedures: an X/Y position measurement and touch detection. Each procedure can be performed by setting the TSI control register (TSICR0 and ...
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Touch Screen Interface (TSI) Control Register 7 Bit symbol TSI7 TSICR0 (002BH) Read/Write R/W After reset 0 Function 0: Disable 1: Enable PXD (Internal Pull-down resistor) ON/OFF setting <PXEN> 0 <TSI7> 0 OFF Bit symbol DBC7 ...
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Touch Detection Procedure A touch detection procedure is a preparing procedure till a pen touches to the screen. When the waiting state, ON only SPY-switch and OFF other 3-switch (SMY, SPX and SMX). During this waiting state, PB5/INT2/PX pin’s ...
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X/Y Position Measuring Procedure In the INT2 routine, execute an X/Y position measuring procedure like below. <X position measurement> At first, ON both SPX and SMX-switches and OFF SPY, SMY-switches. By this setting, analog-voltage which shows the X position ...
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Flow Chart for TSI (1) Touch detection procedure Main routine: TSICR0 ← 98H TSICR1 ← XXH (Voluntary) Execute main routine It shows the circuit for each statement (a), (b) and (c) in the next page. (2) X/Y position measurement ...
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Main routine : Waiting for INT2 interrupt (pbfc)<PB5F>, <PB6F> = “1” (inte12) (tsicr0) = 98h ei TMP91C025 AVCC (PY/PB6) Y+ (PX/PB5/INT2) Touch screen X+ X− (MY/P83) Y− (MX/P82) VREFH VREFL AVSS : Set PB5 to int2/PX, set PB6 to ...
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INT2 routine: X position measurement (AD conversion start) (tsicr0) = 85h (admod1) = 83h (admod0) = 01h TMP91C025 AVCC (PY/PB6) Y+ (PX/PB5/INT2) Touch screen X+ X− (MY/P83) Y− (MX/P82) VREFH VREFL AVSS : Set SMX, SPX to ON. : ...
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INT2 routine: Y position measurement (AD conversion start) (tsicr0) = 8ah (admod1) = 82h (admod0) = 01h TMP91C025 AVCC (PY/PB6) Y+ (PX/PB5/INT2) Touch screen X+ X− (MY/P83) Y− (MX/P82) VREFH VREFL AVSS : Set SMX, SPX to ON. : ...
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Analog/Digital Converter The TMP91C025 incorporates a 10-bit successive approximation type analog/digital converter (AD converter) with 4-channel analog input. Figure 3.11 block diagram of the AD converter. The 4-channel analog input pins (AN0 to AN3) are shared with ...
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Analog/Digital Converter Registers The AD converter is controlled by the two AD mode control registers: ADMOD0 and ADMOD1. The AD conversion results are stored in 8 kinds of AD conversion data upper and lower registers: ADREG04H/L, ADREG15H/L, ADREG26H/L and ...
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ADMOD1 Bit symbol VREFON (02B1H) Read/Write R/W After reset 0 Function VREF IDLE2 application 0: Stop control. 1: Operate 0: Off 1: On Note: As pin AN3 also functions as the < ADTRGE> Figure 3.11.3 AD Converter ...
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ADREG04L Bit symbol ADR01 (02A0H) Read/Write After reset Undefined Function Stores lower 2 bits of AD conversion result. 7 ADREG04H Bit symbol ADR09 (02A1H) Read/Write After reset Function 7 ADREG15L Bit symbol ADR11 (02A2H) Read/Write After reset Undefined Function ...
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Bit symbol ADR21 ADREG26L (02A4H) Read/Write After reset Undefined Function Stores lower 2 bits of AD conversion result. 7 ADREG26H Bit symbol ADR29 (02A5H) Read/Write After reset Function 7 ADREG37L Bit symbol ADR31 (02A6H) Read/Write After reset Undefined Function ...
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Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage as the difference ...
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Starting AD conversion To start AD conversion, write 1 to ADMOD0<ADS> mode control register 0, or ADMOD1<ADTRGE> mode control register 1 and input falling edge on pin. When AD conversion starts, the AD conversion busy ...
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Channel scan repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> selects channel scan repeat conversion mode. In this mode, data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0<EOCF> is set ...
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AD conversion time 84 states (4.7 μ MHz) are required for the AD conversion for one FPH channel. (f) Storing and reading the results of AD conversion The AD conversion data upper and lower registers ...
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Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the AD interrupt (INTAD) processing routine. Main routine ← ...
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Watchdog Timer (Runaway detection timer) The TMP91C025 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (Runaway) due ...
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Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared 0 by software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g. ...
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Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting ...
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WDMOD Bit symbol WDTE WDTP1 (0300H) Read/Write R/W After reset 1 Function WDT Select detecting time. control 00 Enable 01: 2 10: 2 11: 2 Watchdog timer detection time SYSCR1 System Clock Selection <SYSCK> 1 (fs) 0 ...
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WDCR Bit symbol Read/Write (0301H) After reset Read-modify Function B1H: WDT disable code -write 4EH: WDT clear code instructions are prohibited. Figure 3.12.5 Watchdog Timer Control Register − W − B1H 4EH Others 91C025-177 TMP91C025 ...
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Real Time Clock (RTC) 3.13.1 Function Description for RTC 1) Clock function (hour, minute, second) 2) Calendar function (month and day, day of the week, and leap year) 3) 24- or 12-hour (AM/PM) clock function 4) ± 30 second ...
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Control Registers Table 3.13.1 PAGE 0 (Clock function) Registers Symbol Address Bit7 Bit6 SECR 0320H 40 s MINR 0321H 40 min. 20 min. HOURR 0322H DAYR 0323H DATER 0324H MONTHR 0325H YEARR 0326H Year 80 Year 40 Year 20 ...
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Detailed Explanation of Control Register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) 7 SECR Bit symbol (0320H) Read/Write After reset Function ...
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Minute column register (for PAGE0/1) 7 MINR Bit symbol (0321H) Read/Write After reset Function "0" is read MI6 MI5 MI4 Undefined 40 min, 20 min, 10 min, column column column ...
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Hour column register (for PAGE0/1) In case of 24-hour clock mode (MONTHR<MO0> PAGE1 a. 7 HOURR Bit symbol (0322H) Read/Write After reset Function "0" is read case of 12-hour clock mode (MONTHR<MO0> ...
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Day of the week column register (for PAGE0/1) 7 DAYR Bit symbol (0323H) Read/Write After reset Function (5) Day column register (for PAGE0/1) 7 DATER Bit symbol (0324H) Read/Write After reset Function "0" is read "0" ...
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Month column register (for PAGE0 only) 7 MONTHR Bit symbol (0325H) Read/Write After reset Function "0" is read. (7) Select 24-hour clock or 12-hour clock (for PAGE1 only) 7 MONTHR Bit symbol (0325H) Read/Write After reset Function 6 5 ...
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Year column register (for PAGE0 only) 7 YEARR Bit symbol YE7 (0326H) Read/Write After reset Function 80 Years Note: Do not set the data other than showing above. (9) Leap-year register (for PAGE1 only) 7 YEARR Bit symbol (0326H) ...
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PAGE register setting (for PAGE0/1) 7 PAGER Bit symbol INTENA (0327H) Read/Write R/W Read-modify After reset 0 write Function INTRTC instruction 1: Enable are prohibited 0: Disable Note: Please keep the setting order below of <ENATMR>, <ENAAML> and <INTENA>. ...
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Operational description (1) Reading clock data 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can read correctly if reading data after 1Hz interrupt occurred. 2. Using two times reading There is ...
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Writing clock data When a carry over occurs during a write operation, the data cannot be written correctly. Please use the following method to ensure data is written correctly. 1. Using 1Hz interrupt 1Hz interrupt and the count up ...
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Disabling the clock A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in order to prevent malfunction caused by the Carry hold circuit. While the clock is prohibited, the Carry hold circuit holds a one sec. ...
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Explanation of the interrupt signal and alarm signal The alarm function used by setting the PAGE1 register and outputting either of the following three signals from PAGER<PAGE>. INTRTC outputs a 1-shot pulse when the falling edge is detected. RTC ...
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With 1Hz output clock RTC outputs clock of 1Hz to RESTR<DIS1HZ> = “0”, <DIS16HZ>= “1”. RTC also generates an INTRTC interrupt of the falling edge of the clock. (3) With 16Hz output clock RTC outputs clock of 16Hz to ...
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LCD Driver Controller (LCDC) The TMP91C025 incorporates two types liquid crystal display driving circuit for controlling LCD driver LSI. One circuit handles a RAM build-in type LCD driver that can store display data in the LCD driver in itself, ...
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Feature of LCDC of Each Mode Each feature and operation of pin is as follows. Table 3.14.1 Feature of LCDC of Each Mode Shift-register Type LCD Driver Control Common (row): The number of picture elements can be handled Segment ...
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Block Diagram CPU address bus A23 LCDSAH/L Register (10 bits) Internal data bus SCP System clock generate CPU BUSAK Output SR,<BUS1:0> SEG register Internal Data bus To interrupt circuit (Rising edge) 32 kHz clock Timer out TA3OUT ...
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Control Registers 7 LCDSAL Bit symbol SAL15 (0360H) Read/Write R/W After reset 0 Function Display memory address. (Low: A15 to A12) 7 LCDSAH Bit symbol SAL23 (0361H) Read/Write R/W After reset 0 Function 7 LCDSIZE Bit symbol COM3 (0362H) ...
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LCDFFP Bit symbol FP7 (0364H) Read/Write After reset 0 Function 7 − LCDCTL2 Bit symbol (0366H) Read/Write R/W After reset 0 Function Always write to “111”. Note: Please write bit7:5 to “111”, even if you use <RAMBUS>, <AC1> and ...
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Table 3.14.2 Memory Mapping for Direct Addressed Built-in RAM Type Register Address LCDC1L 0FE0H RAM built-in type column driver 1 LCDC1H 0FE1H LCDC2L 0FE2H RAM built-in type column driver 2 LCDC2H 0FE3H LCDC3L 0FE4H RAM built-in type column driver 3 ...
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Shift-register Type LCD Driver Control Mode (SR type) Set the mode of operation, start address of source data save memory and LCD size to control registers before setting start register. After set start register LCDC outputs bus release request ...