TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 73

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Note: After reset, input 1 to PB3 (INT0,
3.5.9
Port B (PB3 to PB6)
input or output. Resetting sets port B to be an input port.
interruption input facility of INT0 to INT3. Edge selection of external interruption is
establishes by IIMC register in the interrupt controller. And also, port B3 has
terminal, and port B4 has clock input terminal TA0IN of 8 bits timer 0, and port B5, B6
each has touch screen block listing PX, PY terminal.
corresponding bits in the port B function register (PBFC). Resetting resets all bits of the
registers PBCR and PBFC to 0, and sets all bits to be input ports.
(1) PB3 (INT0)
Port B3 to PB6 is a 4-bit general-purpose I/O port. Each bit can be set individually for
In addition to functioning as a general-purpose I/O port, port B3 to B6 has each external
Timer output function and external interrupt function can be enabled by writing 1 to the
INT0
PS
Function control
Direction control
Output latch
(on bits basis)
(on bits basis)
PBFC write
PBCR write
PB write
PB read
Reset
S
SYSCR2<PSENV>
PS
Figure 3.5.19 Port B3
) -pin, because it is worked as
Selector
91C025-71
IIMC<I0LE, I0EDGE>
Rising/falling select
S
Level/edge select
A
B
and
PS
input pin.
PB3 (INT0,
TMP91C025
2007-02-28
PS
PS
)
input