TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 127

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
Concurrent
Concurrent
Concurrent
with PC2
with PC2
with PC1
SCLK0
SCLK0
3.9.1
RXD0
f
φT0
SYS
SC0MOD0
<RXE>
Block Diagrams
φ
φ
φ
φ
T0
T2
T8
T32
Figure 3.9.2 is a block diagram representing serial channel 0.
RXDCLK
RB8
I/O interface mode
Serial clock generation circuit
<BR0CK1:0>
BR0CR
Receive buffer 2 (SC0BUF)
2
Receive buffer 1
(UART only ÷ 16)
φT2
(Shift register)
4
Figure 3.9.2 Block Diagram of the Serial Channel 0 (SIO0)
Prescaler
Receive
Receive
counter
control
<BR0S3:0>
8
BR0CR
φT8
16 32 64
Baud rate
generator
<BR0ADDE>
BR0CR
φT32
<OERR><PERR><FERR>
<BR0K3:0>
SC0MOD0
<WU>
BR0ADD
<PE>
Internal data bus
Parity control
SC0CR
Error flag
÷2
SC0CR
91C025-125
Serial channel
<EVEN>
(from TMRA0)
interrupt
TA0TRG
control
SC0MOD0
<SC1:0>
SC0CR
<IOC>
I/O
interface mode
UART
mode
TXDCLK
SC0MOD0
TB8
<SM1:0>
Transmission buffer (SC0BUF)
(UART only ÷ 16)
Transmission
Transmision
counter
control
SIOCLK
SC0MOD0
<CTSE>
TMP91C025
2007-02-28
INT request
INTRX0
INTTX0
Concurrent
with PC2
TXD0
Concurrent
with PC0
CTS
0

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