TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 249

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(8-1) UART/SIO channel 0
(8-2) IrDA
SC0MOD0
BR0ADD
SC0MOD1
SC0BUF
Symbol
Symbol
SC0CR
BR0CR
SIRCR
(8) UART/serial channel (1/2)
Serial
channel 0
buffer
Serial
channel 0
control
Serial
channel 0
mode0
Baud rate
control
Serial
channel0
K setting
register
Serial
channel 0
mode1
IrDA
control
register
Name
Name
Address
Address
(Prohibit
RMW)
200H
201H
202H
203H
204H
205H
207H
Transmission
pulse width.
0: 3/16
1: 1/16
Receiving
data bit8.
Transfer
data bit8.
Always
write 0.
IDLE2
0: Stop
1: Operate
Undefined
RB7/TB7
PLSEL
I2S0
RB8
R/W
R/W
TB8
7
7
R
0
−
0
0
0
1: (16-K)/16
1: CTS
Receiving
data.
0: H pulse
1: L pulse
Parity
0: Odd
1: Even
Duplex
0: Half
1: Full
BR0ADDE
RB6/TB6
enable
FDPX0
RXSEL
divided
enable
EVEN
CTSE
R/W
R/W
6
6
0
0
0
0
0
91C025-247
R/W
1: Receive
Transmission
0: Disable
1: Enable
Parity
enable.
00: φ T0
01: φ T2
10: φ T8
11: φ T32
RB5/TB5
BR0CK1
enable
TXEN
RXE
R/W
PE
5
5
0
0
0
0
R (Receiving)/W (Transmission)
1: Wakeup
Receiving
0: Disable
1: Enable
Over Run
RB4/TB4
BR0CK0
enable
OERR
RXEN
R/W
R (Cleared to 0 by reading.)
WU
4
4
0
0
0
0
Undefined
R/W
R/W
00: I/O Interface
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
Set the effective SIRRxD pulse width
Pulse width more than 2x × (set value + 1) +
100ns
Possible: 1 to 14
Not possible: 0, 15
RB3/TB3
SIRWD3
1: Error
BR0S3
BR0K3
PERR
Parity
SM1
3
3
0
0
0
0
0
Setting the divided frequency “N”
Sets frequency divisor “K”
(Divided by N + (16-K)/16)
RB2/TB2
SIRWD2
Framing
BR0S2
BR0K2
FERR
SM0
2
2
0
0
0
0
0
(0 to F)
R/W
R/W
00: TA0TRG
01: Baud rate generator
10: Internal clock f
11: External clock
0:SCLK0 ↑
1:SCLK0 ↓
RB1/TB1
SIRWD1
SCLKS
BR0S1
BR0K1
SCLK0
SC1
1
1
0
0
0
0
0
TMP91C025
2007-02-28
R/W
1: Input
SCLK0 pin
RB0/TB0
SIRWD0
BR0S0
BR0K0
SC0
IOC
0
0
0
0
0
0
0
SYS