TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 80

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

PD
(0029H)
PDFC
(002AH)
3.5.11
Note: Read-modify-write is prohibited for the registers PDFC.
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Port D (PD0 to PD4, PD7)
PD7 pin output “1”.
controller (D1BSCP, D2BLP, D3BFR, DLEBCD and DOFFB) and output pin for
melody/alarm generator (MLDALM). Above setting is used the function register PDFC.
Port D is a 6-bit output port. Resetting sets the output latch PD to “1”, and PD0 to PD4,
In addition to functioning as output port, port D also function as output pin for LCD
0: Port
1: MLDALM
PD7F
PD7
R/W
W
7
7
1
0
Reset
Output latch
Function control
PDFC write
(on bit basis)
6
6
PD write
Figure 3.5.28 Registers for Port D
PD read
Port D function register
Figure 3.5.27 Port D
5
5
Port D register
91C025-78
D1BSCP, D2BLP, D3BFR,
DLEBCD, DOFFB, MLDALM
0: Port
1: DOFFB
B
A
PD4F
PD4
R/W
W
4
4
1
0
S
Output buffer
0: Port
1: DLEBCD
PD3F
PD3
R/W
W
3
1
3
0
0: Port
1: D3BFR
PD2F
PD2
R/W
W
2
1
2
0
0: Port
1: D2BLP
PD1F
PD0 (D1BSCP),
PD1 (D2BLP),
PD2 (D3BFR),
PD3 (DLEBCD),
PD4 (DOFFB),
PD7 (MLDALM)
PD1
R/W
W
1
1
1
0
0: Port
1: D1BSCP
PD0F
TMP91C025
PD0
R/W
W
0
0
2007-02-28
1
0