TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 61

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.5.3
Port Z (PZ2 to PZ3)
PZFC.
the CPU’s control/status signal.
Port Z is an 2-bit general-purpose I/O port. I/O is set using control register PZCR and
Resetting sets all bits of the output latch PZ to 1.
In addition to functioning as a general-purpose I/O port, port Z also functions as I/O for
Resetting initializes PZ2 and PZ3 pins to input mode with pull-up register.
Function conrtol
Direction control
(on bit basis)
(on bit basis)
PZCR write
PZFC write
Output
PZ write
Reset
latch
S
Figure 3.5.4 Port Z2
HWR
A
B
91C025-59
S
PZ read
Output buffer
P-ch (Programmable pull up)
PZ2 (
HWR
TMP91C025
2007-02-28
)