TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 96

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

System Clock
xxx: Don't care
<SYSCK>
3.7.2
Selection
SYSCR1
1 (fs)
0 (fc)
Operation of Each Circuit
(1) Prescalers
(2) Up counters (UC0 and UC1)
10
Prescaler Clock
the prescaler clock selection register SYSCR0<PRCK1:0>.
timer control register. Setting <TA01PRUN> to 1 starts the count; setting
<TA01PRUN> to 0 clears the prescaler to zero and stops operation. Table 3.7.2 shows
the various prescaler output clock resolutions.
specified by TA01MOD.
the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is
specified by the value set in TA01MOD<TA01CLK1:0>.
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16 or φT256, or the comparator output (The match detection signal) from
TMRA0.
TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up
counters and to control their count. A reset clears both up counters, stopping the
timers.
<PRCK1:0>
(
Selection
A 9-bit prescaler generates the input clock to TMRA01.
The φT0 as the input clock to prescaler is a clock divided by 4 which selected using
The prescaler’s operation can be controlled using TA01RUN<TA01PRUN> in the
SYSCR0
fc/16 CLOCK)
These are 8-bit binary counters which count up the input clock pulses for the clock
The input clock for UC0 is selectable and can be either the external clock input via
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
For
(f
FPH
00
)
each
Table 3.7.2 Prescaler Output Clock Resolution
interval
<GEAR2:0>
Gear Value
100 (fc/16)
SYSCR1
001 (fc/2)
010 (fc/4)
011 (fc/8)
000 (fc)
XXX
XXX
timer
91C025-94
2
2
2
2
2
2
2
the
3
3
4
5
6
7
7
/fs (244 μs)
/fc (0.2 μs)
/fc (0.4 μs)
/fc (0.9 μs)
/fc (1.8 μs)
/fc (3.6 μs)
/fc (3.6 μs)
φT1
timer
Prescaler Output Clock Resolution
2
2
2
2
2
2
2
9
9
5
5
6
7
8
/fc (14.2 μs) 2
/fc (14.2 μs) 2
/fs (977 μs)
/fc (0.9 μs)
/fc (1.8 μs)
/fc (3.6 μs)
/fc (7.1 μs) 2
operation
φT4
at fc = 36 MHz, fs = 32.768 kHz
2
2
2
2
10
11
11
9
7
7
8
/fc (14.2 μs) 2
/fs (3.9 ms) 2
/fc (28.4 μs) 2
/fc (56.9 μs) 2
/fc (56.9 μs) 2
/fc (3.6 μs)
/fc (7.1 μs) 2
control
φT16
2
12
13
14
15
15
register
11
11
TMP91C025
/fc (113.8 μs)
/fc (227.6 μs)
/fc (455.1 μs)
/fc (910.2 μs)
/fc (910.2 μs)
/fs (62.5 ms)
/fc (56.9 μs)
2007-02-28
φT256
bits