TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 146

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Timing to write
transmission data
SCLK0 output
(<SCLKS>=0
Rising edge mode)
ITX0C
(INTTX0
Interrupt request)
SCLK0 output
(<SCLKS>=1
Falling edge mode)
TXD0
(INTTX0
Interrupt request)
TXD0
SCLK0input
(<SCLKS> = 0
Rising edge mode)
SCLK0 input
(<SCLKS> = 1
Falling edge mode)
ITX0C
Figure 3.9.19 Transmitting Operation in I/O Interface Mode (SCLK0 output mode)
Figure 3.9.20 Transmitting Operation in I/O Interface Mode (SCLK0 input mode)
a.
TXD0 and SCLK0 pins respectively each time the CPU writes the data to the
transmission buffer. When all data is output, INTES0<ITX0C> will be set to
generate the INTTX0 interrupt.
input becomes active after the data has been written to the transmission buffer by
the CPU.
interrupt.
Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0
When all data is output, INTES0<ITX0C> will be set to generate INTTX0
Bit0
Bit0
91C025-144
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP91C025
2007-02-28
(Internal clock
timing)