TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 227

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

No.
AC measuring conditions
Note: Symbol “x” in the above table means the period of clock “f
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
(2) Vcc = 2.4 V to 3.6 V
•
•
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
FPH
AC
CAR
CAW
AD
RD
RR
HR
WW
DW
WD
SBA
SWP
SBW
SAS
SWR
SDS
SDH
AW
CW
APH
APH2
APO
Output level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF
Input level:
“f
oscillator frequency.
SYS
f
A0 to 23 valid →
A0 to A23 valid → D0 to D15 input
D0 to D15 valid →
Data byte control access time for SRAM
Write pulse width for SRAM
Data byte control to end of write for SRAM
Address setup time for SRAM
Write recovery time for SRAM
Data setup time for SRAM
Data hold time for SRAM
A0 to A23 valid →
A0 to A23 valid → Port input
A0 to A23 valid → Port hold
A0 to A23 valid → Port valid
RD
RD
RD
RD
RD
WR
WR
WR
FPH
” for CPU core. The period of f
/
rise → A0 to A23 hold
fall → D0 to D15 input
low width
rise → D0 to A15 hold
WR
period ( = x)
rise → A0 to A23 hold
low width
rise → D0 to D15 hold
fall →
High = 0.9 Vcc, Low = 0.1 Vcc
Parameter
WAIT
RD
WAIT
WR
/
WR
hold
rise
input
fall
(1 + N) waits mode
(1 + N) waits mode
FPH
91C025-226
depends on the clock gear setting or selection of high/low
0.5x − 23
2.5x − 15
2.0x − 15
1.5x − 35
1.5x − 35
0.5x − 22
0.5x − 18
2.5x + 0
2x − 15
3x − 25
2x − 35
x − 23
x − 13
x − 25
Min
62.5
3.5x
0
Variable
3.5x − 38
2.5x − 30
3.5x − 60
3.5x − 89
3.5x + 80
3x − 39
31250
Max
FPH
Min
62.5
141
110
110
162
156
218
39
49
58
37
58
90
13
8
0
9
16 MHz
”, it’s half period of the system clock
Max
180
126
148
158
129
298
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMP91C025
2007-02-28