TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 243

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

INTETC01
INTETC23
INTEP01
INTLCD
INTCLR
Symbol
DMA0V
DMA1V
DMA2V
DMA3V
DMAR
DMAB
IIMC
Interrupt control (2/2)
INTLCD
enable
INTTC0
and
INTTC1
enable
INTTC2
and
INTTC3
enable
INTP0 and
INTP1
enable
DMA 0
request
vector
DMA 1
request
vector
DMA 2
request
vector
DMA 3
request
vector
Interrupt
clear
control
DMA
software
request
register
DMA
burst
request
register
Interrupt
input
mode
control
Name
Address
(Prohibit
(Prohibit
(Prohibit
RMW)
RMW)
RMW)
9AH
9BH
9CH
9DH
8AH
8CH
80H
81H
82H
83H
88H
89H
1: INTLCD
Always
write 0.
ILCD2C
ITC1C
ITC3C
IP1C
W
R
R
R
R
7
0
0
0
0
−
0
Always
write 0.
ILCDM2
ITC1M2
ITC3M2
IP1M2
W
6
0
0
0
0
−
0
INTLCD
INTTC1
INTTC3
91C025-241
INTP1
Interrupt level
INT3 edge
0: Rising
1: Falling
DMA0V5
DMA1V5
DMA2V5
DMA3V5
ILCDM1
I3EDGE
ITC1M1
ITC3M1
CLRV5
IP1M1
R/W
R/W
R/W
R/W
W
5
0
0
0
0
0
0
0
0
0
0
Clears interrupt request flag by writing to DMA start vector.
INT2 edge
0: Rising
1: Falling
DMA0V4
DMA1V4
DMA2V4
DMA3V4
ILCDM0
I2EDGE
ITC1M0
ITC3M0
CLRV4
IP1M0
W
4
0
0
0
0
0
0
0
0
0
0
INT1 edge
0: Rising
1: Falling
DMA0V3
DMA1V3
DMA2V3
DMA3V3
I1EDGE
DMAR3
DMAB3
CLRV3
DMA0 Start vector.
DMA1 Start vector.
DMA2 Start vector.
DMA3 Start vector.
ITC0C
ITC2C
IP0C
R/W
R/W
W
R
R
R
3
–
–
–
0
0
0
0
0
0
0
0
0
0
0
1 : DMA request on Burst Mode
R/W
R/W
R/W
R/W
1: DMA request in software
W
INT0 edge
0: Rising
1: Falling
DMA0V2
DMA1V2
DMA2V2
DMA3V2
I0EDGE
ITC0M2
ITC2M2
DMAR2
DMAB2
CLRV2
IP0M2
R/W
R/W
Always write 0
W
2
–
–
0
0
0
0
0
0
0
0
0
0
0
INTTC0
INTTC0
INTP0
–
INT0
0: edge
1:level
DMA0V1
DMA1V1
DMA2V1
DMA3V1
ITC0M1
ITC2M1
DMAR1
DMAB1
CLRV1
IP0M1
I0LE
R/W
R/W
R/W
R/W
R/W
W
0
1
–
–
–
0
0
0
0
0
0
0
0
0
0
TMP91C025
2007-02-28
Always
write 0.
DMA0V0
DMA1V0
DMA2V0
DMA3V0
ITC2M0
ITC0M0
DMAR0
DMAB0
CLRV0
IP0M0
R/W
R/W
W
0
–
–
0
0
0
0
0
0
0
0
0
0
–
0