TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 117
TMP91xy25FG
Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP91XY25FG.pdf
(260 pages)
Specifications of TMP91xy25FG
Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
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3.8.1
Recommendable Memory Map
memory correspondence is shown in Figure 3.8.1. And a physical-address map is shown in
Figure 3.8.2.
section of CS/WAIT controller. Setting of register in MMU is not necessary.
The recommendation logic address memory map at the time of varieties extension
However, when memory area is less than 16 Mbytes and is not expanded, please refer to
Since it is being fixed, the address of a local-area cannot be changed.
Address
000000H
100000H
200000H
400000H
600000H
800000H
C00000H
E00000H
FFFF00
FFFFFF
256 Bytes
2 Mbytes
2 Mbytes
2 Mbytes
4 Mbytes
2 Mbytes
2 Mbytes
1 Mbyte
1 Mbyte
Size
Memory map
COMMON1
COMMON2
Vector area
COMMON0
LOCAL0
LOCAL1
LOCAL3
LOCAL2
Figure 3.8.1 Logical Address Map
91C025-115
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2
0 1 2 3 4 5 6 7
BANK
…
6 7
CS/WAIT
CS3
CS0
CS1
CS2
CS2
setting
: Internal area
: Overlapped with COMMON a
CS
CS
CS
CS
CS
CS
CS
2
2
2
1
A
3
0
pin
B
C
TMP91C025
(BANK 0 to 3)
(BANK 4 to 7)
2007-02-28
rea
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