TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 24

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(2) Clock gear controller
(3) Internal clock output pin
(Example 3)
(High-speed clock gear changing)
(Example)
is set according to the contents of the clock gear select register SYSCR1<GEAR2:0> to
either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f
reduces power consumption.
register.It is necessary the warm-up time until changing after writing the register
value.
instruction is executed by the clock gear before changing.To execute the instruction
next to the clock gear switching instruction by the clock gear after changing,input the
dummy instruction as follows (Instruction to execute the write cycle).
PAFC2<PA3F2> register, the PA3 pin functions as the SCOUT pin.
X: Don't care
SYSCR1
SYSCR1
When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> = 0, f
Changing to a high-frequency gear
To change the clock gear, write the register value to the SYSCR1<GEAR2:0>
There is the possibility that the instruction next to the clock gear changing
An internal clock f
EQU
LD
EQU
LD
LD
Instruction to be executed after clock gear has changed
00E1H
(SYSCR1), XXXX0000B
00E1H
(SYSCR1), XXXX0001B
(DUMMY), 00H
FPH
can be output to the PA3/SCOUT pin. By setting “1” to the
91C025-22
;
;
;
Changes f
Changes f
Dummy instruction
SYS
SYS
to fc/2.
to fc/4.
TMP91C025
2007-02-28
FPH
FPH