TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 46

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
DMAR
Name
request
register
DMA
(2) Soft start function
(3) Transfer control registers
a micro DMA software start function that starts micro DMA on the generation of the
write cycle to the DMAR register.
bits, micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the
DMAR register is automatically cleared to 0.
writing 1. If read 1, micro DMA transfer isn’t started yet.
the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If the
value in the micro DMA transfer counter is 0 after start up of the micro DMA transfer
counter doesn’t change. Don’t use Read-modify-write instruction to avoid writing to
other bits by mistake.
following registers in CPU. Data setting for these registers is done by an LDC cr,r
instruction.
In addition to starting the micro DMA function by interrupts, TMP91C025 includes
Writing 1 to each bit of DMAR register causes micro DMA once (If write 0 to each
Only one-channel can be set for micro DMA at once. (Do not write 1 to plural bits.)
When writing again 1 to the DMAR register, check whether the bit is 0 before
When a burst is specified by DMAB register, data is continuously transferred until
The transfer source address and the transfer destination address are set in the
Address
(Prohibit
RMW)
Channel 0
Channel 3
89H
DMAS0
DMAD0
DMAS3
DMAD3
32 bits
DMAC0
DMAC3
16 bits
7
DMAM0
DMAM3
8 bits
6
91C025-44
DMA source address register 0:
DMA destination address register 0: only use LSB 24 bits.
DMA counter register 0:
DMA mode register 0.
DMA source address register 3.
DMA destination address register 3.
DMA counter register 3.
DMA mode register 3.
5
4
DMAR3
3
0
only use LSB 24 bits.
1 to 65536 .
DMAR2
2
0
DMA request
R/W
DMAR1
1
0
TMP91C025
2007-02-28
DMAR0
0
0