TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 42

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.4.1
General-purpose Interrupt Processing
operations. That is also the same as TLCS-900/L and TLCS-900/H.
(1) The CPU reads the interrupt vector from the interrupt controller.
(2) The CPU pushes the value of program counter (PC) and status register (SR) onto the
(3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1)
(4) The CPU increases the interrupt nesting counter INTNEST by 1 (+1).
(5) The CPU jumps to the address indicated by the data at address FFFF00H + interrupt
When the CPU accepts an interrupt, it usually performs the following sequence of
If the same level interrupts occur simultaneously, the interrupt controller generates an
interrupt vector in accordance with the default priority and clears the interrupt
request.
(The default priority is already fixed for each interrupt: the smaller vector value has
the higher priority level.)
stack area (indicated by XSP).
to the interrupt mask register <IFF2:0>. However, if the priority level of the accepted
interrupt is 7, the register’s value is set to 7.
vector and starts the interrupt processing routine.
The above processing time is 18 states (1.00 μs at 36 MHz) as the best case (16-bit data
bus width and 0 waits).
to the main routine. RETI restores the contents of program counter (PC) and status
register (SR) from the stack and decreases the Interrupt Nesting counter INTNEST by
1 (−1).
interrupts, however, can be enabled or disabled by a user program. A program can set
the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable
an interrupt request.)
the CPU interrupt mask register <IFF2:0> comes out, the CPU accepts its interrupt.
Then, the CPU interrupt mask register <IFF2:0> is set to the value of the priority level
for the accepted interrupt plus 1 (+1).
during its processing, the CPU accepts the later interrupt and goes to the nesting
status of interrupt processing.
(1) to (5) processing steps of the current interrupt, the latest interrupt request is
sampled immediately after execution of the first instruction of the current interrupt
processing routine. Specifying DI as the start instruction disables maskable interrupt
nesting.
maskable interrupts.
The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector
area.
When the CPU compled the interrupt processing, use the RETI instruction to return
Non-maskable interrupts cannot be disabled by a user program. Maskable
If an interrupt request which has a priority level equal to or greater than the value of
Therefore, if an interrupt is generated with a higher level than the current interrupt
Moreover, if the CPU receives another interrupt request while performing the said
A reset initializes the interrupt mask register <IFF2:0> to 111, disabling all
Table 3.4.1 shows the TMP91C025 interrupt vectors and micro DMA start vectors.
91C025-40
TMP91C025
2007-02-28