TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 250

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(8-3) UART/SIO channel 0
SC1BUF
SC1MOD0
SC1MOD1
BR1ADD
Symbol
SC1CR
BR1CR
Clock gear (2/2)
Serial
channel 1
buffer
Serial
channel 1
control
Serial
channel 1
mode
Baud rate
control
Serial
channel 1
K setting
register
Serial
channel 1
mode1
Name
(Prohibit
Address
RMW)
208H
20AH
20BH
20CH
20DH
209H
Receiving
data bit8.
Trans-
mission
data bit8.
Always
write 0.
IDLE2
0: Stop
1: Operate
Undefined
RB7/TB7
I2S1
RB8
R/W
TB8
7
R
0
−
0
0
1: (16 − K)/16
Parity
0: Odd
1: Even
Duplex
0: Half
1: Full
1: CTS
BR1ADDE
RB6/TB6
divided
enable
FDPX1
enable
EVEN
CTSE
R/W
6
0
0
0
0
91C025-248
R/W
1: Receive
1:Parity
00: φ T0
01: φ T2
10: φ T8
11: φ T32
RB5/TB5
BR1CK1
enable
enable
RXE
PE
5
0
0
0
R (Receiving)/W (Transmission)
1: Wakeup
RB4/TB4
Over run
BR1CK0
enable
OERR
WU
R (Cleared to 0 by reading.)
4
0
0
0
Undefined
R/W
R/W
00: I/O interface
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
RB3/TB3
1: Error
BR1S3
BR1K3
PERR
Parity
SM1
3
0
0
0
0
Setting the divided frequency “N”
Sets frequency divisor “K”
(Divided by N + (16-K)/16)
RB2/TB2
Framing
BR1S2
BR1K2
FERR
SM0
2
0
0
0
0
(0 to F)
R/W
00: TA0TRG
01: Baud rate
10: Internal clock f
11: External clock
1: SCLK1 ↓
0: SCLK1 ↑
RB1/TB1
SCLKS
BR1S1
BR1K1
generater
SCLK1
SC1
1
0
0
0
0
TMP91C025
2007-02-28
R/W
1: Input
SCLK1 pin
RB0/TB0
BR1S0
BR1K0
SC0
IOC
0
0
0
0
0
SYS