TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 34

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

♦: After clearing the HALT mode, CPU starts interrupt processing.
○
×: It can not be used to release the HALT mode.
−: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority
*1: Releasing the HALT mode is executed after passing the warm-up time.
Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled
: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT
Status of Received Interrupt
instruction.
level. There is not this combination type.
INTWDT
INT0 to INT3 (Note 1)
INTALM0 to INTALM4
INTTA0 to INTTA3
INTRX0 to INTRX1, TX0 to TX1
INTAD
INTKEY
INTRTC
INTLCD
RESET
status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt
processing is correctly started.
(Example) Releasing IDLE1 mode
Address
8200H
8203H
8206H
8209H
820BH
820EH
820FH
HALT Mode
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
INT0
Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation
LD
LD
LD
EI
LD
HALT
LD
(PBFC), 00H
(IIMC), 00H
(INTE0AD), 06H
5
(SYSCR2), 88H
XX, XX
(Interrupt level) ≥ (Interrupt mask)
IDLE2
Interrupt Enabled
♦
♦
♦
♦
♦
♦
♦
♦
♦
91C025-32
; Sets PB3 to INT0.
; Selects INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets interrupt level to 5 for CPU.
; Sets HALT mode to IDLE1 Mode.
; Halts CPU.
IDLE1 STOP
♦
♦
♦
♦
×
×
×
×
×
♦
♦
Initialize LSI
×
×
×
×
×
×
×
*1
*1
(Interrupt level) < (Interrupt mask)
INT0 interrupt routine
RETI
IDLE2
Interrupt Disabled
○
○
○
○
−
×
×
×
×
IDLE1 STOP
○
○
○
○
−
×
×
×
×
TMP91C025
2007-02-28
○
○
−
×
×
×
×
×
×
*1
*1