TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 149

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

(2) Mode 1 (7-bit UART mode)
(3) Mode 2 (8-bit UART mode)
<SM1:0> to 01.
the setting of the serial channel control register SC0CR<PE> bit; whether even parity
or odd parity will be used is determined by the SC0CR<EVEN> setting when
SC0CR<PE> is set to 1 (Enabled).
parity bit can be added (Use of a parity bit is enabled or disabled by the setting of
SC0CR<PE>); whether even parity or odd parity will be used is determined by the
SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (Enabled).
X: Don’t care, −: No change
P9CR
P9FC
SC0MOD
SC0CR
BR0CR
INTES0
SC0BUF
7-bit UART mode is selected by setting serial channel mode register SC0MOD0
In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by
(Setting example)
When transmitting data of the following format, the control registers should be set
8-bit UART mode is selected by setting SC0MOD0<SM1:0> to 10. In this mode, a
(Setting example)
When receiving data of the following format, the control registers should be set as
as described below. This explanation applies to channel 0.
described below.
∗ Clock state
← X 0 − X 0 1 0 1
← X 1 1 X X X 0 0
← 0 0 1 0 0 1 0 1
← 1 1 0 0 − − − −
← * * * * * * * *
← − − − − − − − 1
← − − − − − − − 1
7 6 5 4 3 2 1 0
Start
Start
Transmission direction (transmission rate: 2400 bps at fc = 12.288 MHz)
Transmission direction (transmission rate: 9600 bps at fc = 12.288 MHz)
Bit0
Bit0
System clock: High-frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: f
1
1
91C025-147
2
2
Select 7-bit UART mode.
Add even parity.
Set the transfer rate to 2400 bps.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Set data for transmission.
Set PC0 to function as the TXD0 pin.
3
3
FPH
4
4
5
5
6
6
parity Stop
Even
7
parity Stop
Odd
TMP91C025
2007-02-28