TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 208

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.14.4.3 Transfer Time by Data Bus Width
3.14.4.4 LCDC Operation in HALT Mode
Note: It need to set the same bus width setting of display RAM, CS/WAIT controller and
D7 to D0
D7 to D0
Address
Address
D1SCP
D1SCP
f
FPH
RD
RD
LCDCTL2<RAMBUS>
LCDCTL<BUS1:0>. And that cycle is selectable, type A, type B and type C. Each type
has each timing, for detail, look for timing table.
width of LCD driver.
setting value of CS/WAIT controller in case of external RAM
mode, LCDC continue operation if CPU in IDLE2 mode. But LCDC stops in case of
IDLE1, STOP mode.
Data bus width of LCD driver can be selected either of BYTE/NIBBLE by
Readout bus width of source is selectable 8 bits or 16 bits, without concern to bus
WAIT number of the read cycle is 0 waits in case of built-in RAM and works by
When LCDC is working, CPU executes HALT instruction and changes in HALT
2states/1byte
Figure 3.14.6 Bus Width Timing (No-wait external RAM)
3 states/1 byte
12H
12H
n
n
12H
x2H
x1H
n + 1
91C025-207
34H
34H
34H
Nibble mode
n + 1
Byte mode
n + 2
56H
x4H
x3H
56H
n + 3
78H
56H
n + 2
78H
x6H
TMP91C025
2007-02-28
x5H
n + 4
9aH