TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 12

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.
3.1
3.1.1
Operation
this manual.
This following describes block by block the functions and operation of the TMP91C025.
Notes and restrictions for eatch book are outlined in 6, precautions and restrictions at the end of
CPU
operation, see the TLCS-900/L1 CPU.
functions are not covered in the TLCS-900/L1 CPU section.
The TMP91C025 incorporates a high-performance 16-bit CPU (the 900/L1-CPU). For CPU
The following describe the unique function of the CPU used in the TMP91C025; these
Reset
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the
36 MHz).
voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the
mode f
RESET
When resetting the TMP91C025 microcontroller, ensure that the power supply voltage is
Thus, when turn on the switch, be set to the power supply voltage is within the operating
Clock gear is initialized 1/16 mode by reset operation. It means that the system clock
When the reset is accept, the CPU:
Figure 3.1.1 is a reset timing chart of the TMP91C025.
•
•
•
•
•
program counter settings. CPU internal registers not mentioned above do not change
when the reset is released.
follows.
•
•
Note: The CPU internal register (Except to PC, SR, XSP) do not change by resetting.
When reset is released,the CPU starts executing instructions in accordance with the
When the reset is accepted, the CPU sets internal I/O, ports, and other pins as
SYS
input to low level at least for 10 system clocks.
Sets as follows the program counter (PC) in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
Sets the stack pointer (XSP) to 100H.
Sets bits <IFF2:0> of the status register (SR) to 111 (Sets the interrupt level mask
register to level 7).
Sets the <MAX> bit of the status register (SR) to 1 (MAX mode).
Note: As this product does not support MIN mode, do not write a 0 to the <MAX>
Clears bits <RFP2:0> of the status register(SR) to 000 (Sets the register bank to
0 ).
Initializes the internal I/O registers.
Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
PC<0:7>
PC<15:8>
PC<23:16>
is set to fc/32(= fc/16 × 1/2).
← Value at FFFF00H address
← Value at FFFF01H address
← Value at FFFF02H address
RESET
91C025-10
input to low level at least for 10 system clocks (9 μs at
TMP91C025
2007-02-28