TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 36

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

<RSYSCK>
SYSCR0
Interrupt for
0 (fc)
1 (fs)
D0 to D15
A0 to A23
Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt
release
c.
Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode
WR
RD
X1
STOP mode
oscillator pin status in STOP mode depends on the settings in the
SYSCR2<DRVE> register. Table 3.3.6, Table 3.3.7 summarizes the state of these
pins in STOP mode.
warm-up time has elapsed, in order to allow oscillation to stabilize. After STOP
mode has been cleared, either NORMAL mode or SLOW mode can be selected
using the SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN> and
<RXTEN> must be set see the sample warm-up times in Table 3.3.5.
an interrupt.
When STOP mode is selected, all internal circuits stop, including the internal
After STOP mode has been cleared system clock output starts when the
Figure 3.3.8 illustrates the timing for clearance of the STOP mode halt state by
01 (2
7.1 μs
7.8 ms
Data
8
)
91C025-34
SYSCR2<WUPTM1:0>
STOP
mode
0.455 ms
10 (2
500 ms
Warm-up
time
14
)
at f
OSCH
= 36 MHz, fs =32.768 kHz
1.820 ms
11 (2
2000 ms
16
)
TMP91C025
2007-02-28
Data