TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 76

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
PB
(0022H)
PBCR
(0024H)
PBFC
(0025H)
Note 1: Output latch register is set to 1.
Note 2: Read-modify-write is prohibited for the registers PBCR and PBFC.
Note 3: PB4/TA0IN pins do not have a register changing port/function .
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
For example, when it is used as an input port, the input signal is inputted to 8-bit timer 0 as the timer input 0.
7
7
7
0: Port
1: INT3
PB6F
PB6
6
6
6
0
Figure 3.5.22 Registers for Port B
Data from external port (Note 1).
Port B Function Register
0: Port
1: INT2
Port B Control Register
PB5F
PB5
5
5
5
0
Port B Register
91C025-74
R/W
W
0: Input
1: Output
0: Port
1:
PB4C
PB4F
INT1
PB4
4
4
4
0
0
W
0: Port
1: INT0
PB3C
PB3F
PB3
3
3
0
3
1
2
2
2
1
1
1
TMP91C025
0
0
0
2007-02-28

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