TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 108

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

TMRA0 comparator match
detect signal
TMRA0 comparator match
detect signal
TA1OUT
INTTA0
INTTA1
Value of up counter
(UC1, UC0)
(2) 16-bit timer mode
(Setting example)
To generate an INTTA1 interrupt every 0.22 s at fc = 36 MHz, set the timer registers
TA0REG and TA1REG as follows:
(Example)
When TA1REG = 04H and TA0REG = 80H
TMRA1.
set TA01MOD<TA01M1:0> to 01.
TMRA1, regardless of the value set in TA01MOD<TA01CLK1:0>. Table 3.7.2 shows
the relationship between the timer (Interrupt) cycle and the input clock selection.
TA0REG first because setting data for TA0REG inhibit its compare function and
setting data for TA1REG permit it.
value in the registers: 0.22 s/(2
matches TA0REG, though the up counter UC0 is not be cleared and also INTTA0 is not
generated.
comparator pulse on which the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparators
TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt
INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop
TA1FF is inverted.
A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for
LSB 8-bit set to TA0REG and MSB 8-bit is for TA1REG. Please keep setting
If φT16 ((2
(i.e. set TA1REG to F4H and TA0REG to 24H).
As a result, INTTA1 interrupt can be generated every 0.23 [s].
The comparator match signal is output from TMRA0 each time the up counter UC0
In the case of the TMRA1 comparator, the match detect signal is output on each
∗ Clock state
Figure 3.7.12 Timer Output by 16-Bit Timer Mode
7
System clock: High-frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: f
/fc)s at 36 MHz) is used as the input clock for counting, set the following
0080H
FPH
91C025-106
7
/fc) μs ≈ 62500 = F424H
0180H
0280H
0380H
0480H
Inversion
0080H
TMP91C025
2007-02-28