TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 191
TMP91xy25FG
Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP91XY25FG.pdf
(260 pages)
Specifications of TMP91xy25FG
Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
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3.
Disabling the clock
order to prevent malfunction caused by the Carry hold circuit. While the clock is
prohibited, the Carry hold circuit holds a one sec. carry signal from a divider.
When the clock becomes enabled, the carry signal is output to the clock, the time
is revised and operation continues. However, the clock is delayed when
clock-disabled state continues for one second or more. Note that at this time
system power is down while the clock is disabled. In this case the clock is stopped
and clock is delayed.
the clock is stopped and time is delayed.
A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in
During clock disabling, pay attention with system power is downed. In this case
Figure 3.13.4 Flowchart of Clock disable
Read the clock data
91C025-190
Disable the clock
Enable the clock
Start
End
TMP91C025
2007-02-28
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