TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 197

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

LCDSAL
(0360H)
LCDSAH
(0361H)
LCDSIZE
(0362H)
LCDCTL
(0363H)
Note 1: There is a limitation about to set LCDSAH and LCDSAL start address.
Note 2: Initial incrementer’s address (LSB 14 bits) for LCDC DMA is 0000 (hex).
3.14.3
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
It prohibit to set A13 carry to A14 by all 1-frame data transmitting.
Start address of LCDC: SAL15 to SAL12 = 0000 or 0001;
Control Registers
e.g. In case 240 (Row) × 360 (Column): 2a30 bytes
(SR,RAM
mode)
0: Off
1: On
DOFF
LCD common number. (SR mode)
0000: 64
0001: 68
0010: 80
0011: 100
0100: 120
LCDON
SAL15
SAL23
Display memory address. (Low: A15 to A12)
COM3
R/W
R/W
R/W
R/W
7
7
7
7
0
0
0
0
Always
write 0.
SAL14
SAL22
COM2
R/W
R/W
R/W
R/W
0101: 128
0110: 144
0111: 160
1000: 200
1001: 240 Other: Reserved
6
6
6
6
0
0
0
−
0
SR mode
Always
write 0.
Display memory address. (High: A23 to A16)
SAL13
SAL21
COM1
R/W
R/W
R/W
R/W
LCDSIZE Register
5
5
LCDSAH Register
5
5
−
0
0
0
0
LCDSAL Register
LCDCTL Register
91C025-196
Data bus width.
(SR mode)
00: 8 bits (Byte mode)
01: 4 bits (Nibble mode)
10: Reserved
11: Reserved
SAL12
SAL20
COM0
BUS1
R/W
R/W
R/W
R/W
4
4
4
4
0
0
0
0
SR mode
LCD segment number. (SR mode)
0000: 32
0001: 64
0010: 80
0011: 120
0100: 128
SAL19
SEG3
BUS0
R/W
R/W
R/W
3
3
3
3
0
0
0
MMULCD
Type
selection
LCDD (build
in RAM).
0: Sequential
1: Random
Always
write 0.
SAL18
SEG2
R/W
R/W
R/W
R/W
0101: 160
0110: 240
0111: 320
1000: 360
Other: Reserved
2
2
2
2
0
−
0
0
0
Setting bit8
for f
Always
write 0.
SAL17
SEG1
FP8
R/W
FP
R/W
R/W
R/W
1
0
1
1
1
−
0
0
0
.
Start
control.
(SR mode)
0: Stop
1: Start
Mode
select
0: RAM
1: SR
START
MODE
SAL16
SEG0
R/W
R/W
R/W
R/W
TMP91C025
0
0
0
0
0
0
0
0
2007-02-28