TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 151

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

a.
b.
c.
d.
e.
f.
Protocol
Select 9-bit UART mode on the master and slave controllers.
Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving.
The master controller transmits one-frame data including the 8-bit select code for
the slave controllers. The MSB (bit8)<TB8> is set to 1.
Each slave controller receives the above frame. Each controller checks the above
select code against its own select code. The controller whose code matches clears
its WU bit to 0.
The master controller transmits data to the specified slave controller whose
SC0MOD<WU> bit is cleared to 0. The MSB (bit8) <TB8> is cleared to 0.
The other slave controllers (whose <WU> bits remain at 1) ignore the received
data because their MSBs (Bit8 or <RB8>) are set to 0, disabling INTRX0
interrupts.
The slave controller (WU bit = 0) can transmit data to the master controller, and it
is possible to indicate the end of data receiving to the master controller by this
transmission.
Start
Start
Bit0
Bit0
1
1
Select code of slave controller
91C025-149
2
2
3
3
Data
4
4
5
5
6
6
7
7
Bit8
1
0
8
Stop
Stop
TMP91C025
2007-02-28