TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 114

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
Select System
<SYSCK>
SYSCR1
8-bit timer × 2 channels
16-bit timer mode
8-bit PPG × 1 channel
8-bit PWM × 1 channel
8-bit timer × 1 channel
XXX: Don’t care
−: Don’t care
Clock
1 (fs)
0 (fc)
Register Name
<Bit Symbol>
Function
Select Prescaler
10 (fc/16 clock)
(5) Settings for each mode
<PRCK1:0>
SYSCR0
00 (f
Clock
FPH
Table 3.7.4 shows the SFR settings for each mode.
)
<TA01M1:0>
Timer Mode
<GEAR2:0>
00
01
10
11
11
Gear Value
XXX
000 (fc)
001 (fc/2)
010 (fc/4)
011 (fc/8)
100 (fc/16)
XXX
SYSCR1
Table 3.7.4 Timer Mode Setting Registers
<PWM01:00> <TA1CLK1:0> <TA0CLK1:0>
PWM Cycle
Table 3.7.3 PWM Cycle
(01, 10, 11)
15.6 ms
14.2 μs
28.4 μs
56.8 μs
113 μs
227 μs
227 μs
2
φT1
6
, 2
91C025-112
7
, 2
TA01MOD
8
62.5 ms
56.8 μs
113 μs
227 μs
455 μs
910 μs
910 μs
φT4
2
6
Lower timer match
φT1, φT16 , φT256
φT1, φT16, φT256
Upper Timer
(00, 01, 10, 11)
Input Clock
1820 μs
3640 μs
3640 μs
φT16
250 ms
227 μs
455 μs
910 μs
(01, 10, 11)
31.3 ms
28.4 μs
56.8 μs
113 μs
227 μs
455 μs
455 μs
φT1
PWM Cycle
1820 μs
1820 μs
125 ms
Lower Timer
(00, 01, 10, 11)
(00, 01, 10, 11)
(00, 01, 10, 11)
(00, 01, 10, 11)
113 μs
227 μs
455 μs
910 μs
φT1, φT4, φT16
φT1, φT4, φT16
φT1, φT4, φT16
φT1, φT4, φT16
Input Clock
External clock
External clock
External clock
External clock
φT4
2
7
1820 μs
3640 μs
7281 μs
7281 μs
500 ms
φT16
455 μs
910 μs
at fc = 36 MHz, fs = 32.768 kHz
62.5 ms
56.8 μs
113 μs
227 μs
455 μs
910 μs
910 μs
0: Lower timer output
1: Upper timer output
φT1
Timer F/F Invert
Signal Select
Output disabled
TA1FFCR
TA1FFIS
TMP91C025
3640 μs 14563 μs
1820 μs
3640 μs 14563 μs
250 ms
2007-02-28
227 μs
455 μs
910 μs
φT4
2
8
1000 ms
1820 μs
3640 μs
7281 μs
φT16
910 μs

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