TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 201

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

LCDCTL
(0363H)
LCDFFP
(0364H)
3.14.4.1 Settlement of Frame Frequency Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
value set in f
usually outputs the signal inverts polarity every frame period.
setting mentioned before. However this f
number, frame period can be corrected by increasing f
3.14.5.
Note: Please make the value set to f
Example:
(SR, RAM
mode)
0: Off
1: On
TMP91C025 defines so-called frame period (Refresh interval for LCD panel) by the
Basic frame period: DLEBCD signal, is made according to the resister f
The equation can calculate frame period.
Frame period = LCDCK/ (D x f
Please select the value of f
DOFF
LCDON
R/W
FP7
7
7
0
0
COM (Common number) ≤ FR ≤ 320
Always
write 0.
In the case where frame period is set to 72.10 Hz by 240 coms.
f
Therefore, LCDCTL<FP8> = 1 and LCDFFP<FP7:0> = 2FH are setup.
FP
FP
FP6
R/W
6
= 240 (COM) + 63 = 303 = 12FH (by Table 3.14.5)
6
0
−
0
[8:0]. DLEBCD pin outputs pulse every frame period. DLEBFR pin
Always
write 0.
R/W
FP5
5
5
0
LCDCTL Register
−
0
LCDFFP Register
91C025-200
FP
Setting bit7 to bit0 for f
Data bus width.
(SR mode)
00: 8 bits (Byte mode)
01: 4 bits (Nibble mode)
10: Reserve
11: Reserve
[8:0] as the frame period you want to set in the Table
FP
BUS1
R/W
FP4
4
4
0
0
) [Hz] D: Constant for each common (Table 3.14.5)
FP
R/W
[8:0] into the following range.
FP
f
LCDCK: Source clock of LCD
(Low clock is usually selected )
BUS0
R/W
FP3
FP
[8:0] setting is generally equal to common
3
3
0
0
: Setting of f
FP
.
TYPE
selection
LCDD (Build
in RAM).
0:Sequential
1:Random
MMULCD
FP2
R/W
FP
2
0
2
0
[8:0] with ease.
FP
Setting bit
8 for f
[8:0] resister
FP1
FP8
R/W
1
0
1
0
FP
.
Start
control.
(SR mode)
0: Stop
1: Start
START
R/W
FP0
TMP91C025
0
0
0
0
2007-02-28
FP
[8:0]