TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 198

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

LCDFFP
(0364H)
LCDCTL2
(0366H)
Note:
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Please write bit7:5 to “111”, even if you use <RAMBUS>, <AC1> and <AC0> as initial setting.
LCDC1L/LCDC1H/LCDC2L/LCDC2H/LCDC3L/LCDC3H/LCDR1L/LCDR1H Register
and display registers of external RAM built-in sequential access type (Note) LCD driver.
becomes active when accesses corresponding address.
external access. Table 3.14.3 shows the address map in the case of controlling RAM built-in
random access type (Note) LCD driver.
LCDCTL<MMULCD>.
These registers do not exist on TMP91C025. These are image for instruction registers
Address as Table 3.14.2 is assigned to these registers, and the following chip enable pin
And, the area of these address is external area, so
The explanation part of MMU circuit also explains this. This setup is performed by
Always write to “111”.
R/W
FP7
D7
7
7
7
0
−
0
R/W
FP6
D6
6
6
6
0
−
0
Depend on the specification of external LCD driver.
Depend on the specification of external LCD driver.
Depend on the specification of external LCD driver.
R/W
FP5
LCDCTR2 Register
D5
5
5
5
0
−
0
LCDFFP Register
91C025-197
Setting bit7 to bit0 for f
FP4
D4
4
4
4
0
R/W
FP3
D3
3
3
3
0
FP
RD
.
0: Byte
1: Word
RAMBUS
R/W
,
FP2
D2
2
2
2
0
WR
0
terminal becomes active by
00: Type A
01: Type B
10: Type C
11: Reserved
R/W
AC1
FP1
D1
1
1
1
0
0
R/W
AC0
FP0
TMP91C025
D0
0
0
0
0
0
2007-02-28