TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 176

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

3.12.2
WDT counter
WDT interrupt
Internal reset
WDT counter
WDT interrupt
Operation
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared 0 by software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g. if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (Runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-malfunction
program.
continues counting during bus release (When
<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters IDLE2
mode.
(f
f
device. In this case, the reset time will be between 22 and 29 states (19.6 to 25.8 μs at f
= 36MHz, f
oscillator clock (f
SYS
SYS
The watchdog timer generates an INTWD interrupt when the detection time set in the
The watchdog timer works immediately after reset.
The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter
When the device is in IDLE2 mode, the operation of WDT depends on the WDMOD
The watchdog timer consists of a 22-stage binary counter which uses the system clock
The runaway is detected when an overflow occurs, and the watchdog timer can reset
WDT clear
(Software)
/2
) as the input clock. The binary counter can output f
21
.
OSCH
n
= 2.25 state )is f
OSCH
n
) by sixteen through the clock gear function.
Figure 3.12.2 Normal Mode
Figure 3.12.3 Reset Mode
Overflow
(19.6 to 25.8 μs at f
91C025-174
FPH
/2, where f
Over flow
OSCH
22 to 29 states
BUSAK
= 36 MHz, f
FPH
is generated by dividing the high-speed
goes low).
Write clear code
FPH
= 2.25 MHz)
SYS
/2
15
, f
SYS
/2
17
, f
TMP91C025
2007-02-28
SYS
/2
0
19
and
FPH