MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 998
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
PCI Bus Interface
17.3.1.1
The PCI configuration header, shown in
utilizing a pair of 32-bit memory-mapped access registers. For PCI, CFG_ADDR is at offset 0x000 and
CFG_DATA is at offset 0x004.
17.3.1.1.1
The CFG_ADDR register is shown in
Table 17-4
Bus number 0xb00 and device number 0b0_0000 are used to configure the internal PCI configuration
header of the PCI controller itself.
17-14
0xE28–
0xF00–
0xEFC
Offset
0xE0C
0xE1C
0xFFC
0xE10
0xE14
0xE18
0xE20
Offset 0x000
Reset
W
R
EN
0
16–20 Device Number
21–23 Function Number
24–29 Register Number
30–31 —
8–15
Bits
1–7
ERR_ATTRIB—PCI error attributes capture register
ERR_ADDR—PCI error address capture register
ERR_EXT_ADDR—PCI error extended address capture register
ERR_DL—PCI error data low capture register
ERR_DH—PCI error data high capture register
GAS_TIMR—PCI gasket timer register
Reserved
Reserved for debug
describes the bit settings for the CFG_ADDR register.
0
1
PCI Configuration Access Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Configuration Address Register (CFG_ADDR)
Bus Number
Enable
—
—
Name
Table 17-3. PCI Memory-Mapped Register Map (continued)
7
Table 17-4. PCI CFG_ADDR Field Descriptions
8
Figure 17-3. PCI CFG_ADDR Register
Register
Allow a PCI configuration access when PCI CFG_DATA is accessed
Reserved
PCI bus number to access
Device number to access on specified bus
Function to access within specified device
32-bit register to access within specified device
Reserved, hardwired to logic 00
Bus Number
Figure
Figure 17-24
17-3.
All zeros
15 16
and
Device Number
Figure
Description
17-58, is accessed via an indirect method
20 21
Access
Function
R/W
R/W
R/W
R/W
R/W
R/W
Number
—
—
23 24
0x0100_3FFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Register Number
—
—
Freescale Semiconductor
Access: Read/Write
17.3.1.4.4/17-27
17.3.1.4.5/17-28
17.3.1.4.6/17-28
17.3.1.4.7/17-29
17.3.1.4.8/17-29
17.3.1.4.9/17-29
Section/page
29 30 31
—
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