MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 340
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 340 of 1340
- Download datasheet (12Mb)
DDR Memory Controller
9.4.1.5
DDR SDRAM timing configuration register 1, shown in
between various SDRAM control commands.
Table 9-10
9-16
Offset 0x108
Reset
20–23
24–27
28–31
Bits
Bits
0
W
R
— PRETOACT
0
ODT_PD_EXIT ODT powerdown exit timing (t
Name
1
MRS_CYC
—
describes TIMING_CFG_1 fields.
Name
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved, should be cleared.
3
Figure 9-6. DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)
4
ACTTOPRE
before ODT may be asserted.
0000 0 clock
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Reserved, should be cleared.
Mode register set cycle time (t
Register Set command until any other command.
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 7 clocks
Table 9-9. TIMING_CFG_0 Field Descriptions (continued)
Table 9-10. TIMING_CFG_1 Field Descriptions
7
— ACTTORW
8
9
11 12
AXPD
MRD
CASLAT
). Specifies how many clocks must pass after exiting powerdown
). Specifies the number of cycles that must pass after a Mode
All zeros
15 16
Description
Figure
Description
REFREC
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
1000 8 clocks
1001 9 clocks
1010 10 clocks
1011 11 clocks
1100 12 clocks
1101 13 clocks
1110 14 clocks
1111 15 clocks
9-6, sets the number of clock cycles
19 20 21
— WRREC — ACTTOACT — WRTORD
23 24 25
Freescale Semiconductor
Access: Read/Write
27 28 29
31
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