MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 595
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
12.7
The SEC may be disabled by setting DEVDISR[SEC]. (See
(DEVDISR),”
should not be enabled/disabled during normal operation.
Freescale Semiconductor
48–55 CHN3_BUS_PR_CNT Channel 3 bus priority counter.This counter is used by the controller to determine when
56–63 CHN4_BUS_PR_CNT Channel 4 bus priority counter. This counter is used by the controller to determine when
Bits
Power-Saving Mode
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Name
for more information on this register.). The clocks to the SEC are active by default. The SEC
Table 12-62. Master Control Register (MCR) Field Descriptions (continued)
Channel 3 has been denied access to the bus long enough to warrant immediate elevation to
top priority.
Note: If set to zero, the CHN4_BUS_PR_CTR must also be set to zero, and the controller will
Channel 4 has been denied access to a needed on-chip resource long enough to warrant
immediate elevation to top priority.
Note: If set to zero, the CHN3_BUS_PR_CTR must also be set to zero, and the controller will
assign access to the bus on a pure round robin basis. If set to non-zero,
CHN4_BUS_PR_CTR must also be set to a different, non-zero value.
assign access to the bus on a pure round robin basis. If set to non-zero,
CHN3_BUS_PR_CTR must also be set to a different, non-zero value.
Section 21.4.1.12, “Device Disable Register
Description
Security Engine (SEC) 2.1
12-115
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