MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 247

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.11.2
Freescale Semiconductor
Reset
56–61
32–46
49–51
SPR 1011
Bits
Bits
55
62
63
47
48
52
W
R
32
ICSLC Instruction cache snoop lock clear. Sticky bit set by hardware if an icbi snoop (either internally or externally
Name
Name
CLFR (Data) Cache lock bits flash reset. Writing a 1 during a flash clear operation causes an undefined operation.
ICPE
ICPI
CFI
CE
—
—
—
L1 Cache Control and Status Register 1 (L1CSR1)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Writing a 0 during a flash clear operation is ignored. Clearing occurs regardless of the enable (CE) value.
0 Default.
1 Hardware initiates a cache lock bits flash clear operation. This bit is cleared when the operation is
Reserved, should be cleared.
(Data) Cache flash invalidate.
0 No cache invalidate. Writing a 0 to CFI during an invalidation operation is ignored.
1 Cache invalidation operation. A cache invalidation operation is initiated by hardware. Once complete, this
Invalidation occurs regardless of the enable (CE) value.
(Data) Cache enable
0 The cache is neither accessed or updated.
1 Enables cache operation
Reserved, should be cleared.
Instruction cache parity enable
0 Parity checking of the instruction cache disabled
1 Parity checking of the instruction cache enabled
Instruction parity error injection enable
0 Parity error injection disabled
1 Parity error injection enabled. Note that instruction cache parity must also be enabled (ICPE = 1) when this
Reserved, should be cleared.
generated) invalidated a locked line in the instruction cache. Note that the lock bit for that line is cleared
whenever the line is invalidated. This bit can only be cleared by software.
0 The instruction cache has not encountered an icbi snoop that invalidated a locked line.
1 The instruction cache has encountered an icbi snoop that invalidated a locked line.
complete.
bit is cleared. Writing a 1 during an invalidation operation causes an undefined operation.
bit is set.
Figure 6-35. L1 Cache Control and Status Register 1 (L1CSR1)
—
Table 6-20. L1CSR0 Field Descriptions (continued)
Table 6-21. L1CSR1 Field Descriptions
46
ICPE ICPI
47
48
All zeros
49
—
Description
Description
51
ICSLC ICUL ICLO ICLFR
52
Line Locking Bits
53
54
55
Access: Supervisor read/write
56
Core Register Summary
—
61
ICFI ICE
62
6-29
63