MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 237
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
6.7.1.8
Freescale Semiconductor
32–35
Bits
Reset
36
37
38
39
40
SPR 62
W
R
32
Name
PPR
PTR
PIL
ST
—
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
35
Exception Syndrome Register (ESR)
IVOR16–IVOR31
IVOR36–IVOR63
Reserved, should be cleared.
Illegal instruction exception
Privileged instruction exception
Trap exception
Reserved and permanently cleared because the e500 does not implement this FPU.
Setting it has no effect.
Store operation
PIL
IVOR Number
36
IVOR10
IVOR11
IVOR12
IVOR13
IVOR14
IVOR15
IVOR32
IVOR33
IVOR34
IVOR35
IVOR5
IVOR6
IVOR8
PPR
37
Figure 6-22. Exception Syndrome Register (ESR)
PTR — ST — DLK
38
Table 6-11. IVOR Assignments (continued)
39
Table 6-12. ESR Field Descriptions
SPR
40
405
406
408
410
411
412
413
414
415
528
529
530
531
—
—
41
Alignment
Program
System call
Decrementer
Fixed-interval timer interrupt
Watchdog timer interrupt
Data TLB error
Instruction TLB error
Debug
Reserved for future architectural use
SPE unavailable
Floating-point data exception
Floating-point round exception
Performance monitor
Allocated for implementation-dependent use
42
Syndrome
ILK
43
All zeros
44
—
45
Interrupt Type
BO
46
47
—
55
Access: Supervisor read/write
SPE
56
Core Register Summary
—
Program
Program
—
Alignment, data
storage, data TLB
error
Program
Interrupt Types
57
—
6-19
63
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