MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 291
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Table 7-15
Figure 7-19
Table 7-16
Freescale Semiconductor
Offset 0x2_0E40
Reset
1–26
Bits
W
27
28
29
30
31
R
0
MULL2ERR
MBECCERR Multiple-bit ECC error (bit reset, write 1 to clear)
SBECCERR Single-bit ECC error (bit reset, write 1 to clear)
MULL2ERR Multiple L2 errors (bit reset, write 1 to clear)
L2CFGERR L2 configuration error (bit reset, write 1 to clear)
W1c
TPARERR
0
describes L2CAPTECC fields.
describes L2ERRDET fields.
Name
shows the L2 error detect register (L2ERRDET).
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
24–31 ECCCHKSUM The data path ECC of the failing double word
8–23
Bits
0–7
0 Multiple L2 errors of the same type were not detected
1 Multiple L2 errors of the same type were detected
Reserved
Tag parity error (bit reset, write 1 to clear)
0 Tag parity error was not detected
1 Tag parity error was detected
Note that if an L2 cache tag parity error occurs on an attempt to write a new line, the L2 cache must
be Flash invalidated. L2 functionality is not guaranteed if Flash invalidation is not performed after a
tag parity error.
0 Multiple-bit ECC errors were not detected
1 Multiple-bit ECC errors were detected
0 Single-bit ECC error was not detected
1 Single-bit ECC error was detected.
Reserved
0 L2 configuration errors were not detected
1 L2 illegal configuration error detected. Reports inconsistencies between the L2SRAM,
L2STASHDIS and L2STASHCTL fields of the L2 control register (L2CTL)
ECCSYND
Figure 7-19. L2 Error Detect Register (L2ERRDET)
Name
—
Table 7-15. L2CAPTECC Field Descriptions
Table 7-16. L2ERRDET Field Descriptions
—
The calculated ECC syndrome of the failing double word
Reserved
All zeros
Description
Description
26
TPARERR MBECCERR SBECCERR
w1c
27
w1c
28
L2 Look-Aside Cache/SRAM
w1c
29
Access: W1c
30
—
L2CFGDIS
w1c
31
7-21
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