MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 253

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.12.5
6.12.5.1
6.12.5.2
Freescale Semiconductor
Reset
Reset
32–34
36–43
44–47
48–62
SPR 624
SPR 625
Bits
35
63
W
W
R
R
32
32
V IPROT
—
TLBSEL
Name
ESEL
NV
33
—
—
—
34
Table 6-28. MAS0 Field Descriptions—MMU Read/Write and Replacement Control
MMU Assist Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MAS Register 0 (MAS0)
TLBSEL
MAS Register 1 (MAS1)
34
35
Reserved, should be cleared.
Selects TLB for access
0 TLB0
1 TLB1
Reserved, should be cleared.
Entry select. Number of entry in selected array to be used for tlbwe. This field is also updated on TLB
error exceptions (misses), and tlbsx hit and miss cases. Only certain bits are valid, depending on the array
selected in TLBSEL. Other bits should be 0.
For the e500, ESEL serves as the way select for the corresponding TLB as follows:
When TLBSEL = 00 (TLB0 selected), bits 46–47 are used (and bits 44–45 should be cleared). This field
selects between way 0, 1, 2, or 3 of TLB0. EA bits 45–51 from MAS2[EPN] are used to index into the TLB
to further select the entry for the operation. Note that for the e500v1, bit 47 selects either way 0 or way 1,
and bit 46 should remain cleared.
When TLBSEL = 01 (TLB1 selected), all four bits are used to select one of 16 entries in the array.
Reserved, should be cleared.
Next victim. Next victim bit value to be written to TLB0[NV] on execution of tlbwe. This field is also updated
on TLB error exceptions (misses), tlbsx hit and miss cases and on execution of tlbre.
This field is updated based on the calculated next victim bit for TLB0 (based on the round-robin
replacement algorithm.)
Note that this field is not defined for operations that specify TLB1 (when TLBSEL = 01).
36
—
39 40
—
Figure 6-43. MAS Register 0 (MAS0)
Figure 6-44. MAS Register 1 (MAS1)
43 44
TID
ESEL
All zeros
All zeros
47 48
47 48
Descriptions
—
50 51 52
TS
TSIZE
—
55 56
Access: Supervisor read/write
Access: Supervisor read/write
Core Register Summary
—
62
NV
6-35
63
63