MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 476
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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I
11.5.2
After initialization, the following sequence can be used to generate START:
The scenario above assumes that the I
an I
I
one interrupt, which is sourced by the dual I
11.5.3
Transmission or reception of a byte automatically sets the data transferring bit (I2CSR[MCF]), which
indicates that one byte has been transferred. The I
is generated to the processor if the interrupt function is enabled during the initialization sequence
(I2CCR[MIEN] is set). In the interrupt handler, software must take the following steps:
When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If master
receive mode is required, I2CCR[MTX] must be toggled at this stage. See
Service Routine Flowchart.”
If the interrupt function is disabled, software can service the I2CDR in the main program by monitoring
I2CSR[MIF]. In this case, I2CSR[MIF] must be polled rather than I2CSR[MCF] because MCF behaves
differently when arbitration is lost. Note that interrupt or other bus conditions may be detected before the
I
may be needed in order to give the I
During slave-mode address cycles (I2CSR[MAAS] is set), I2CSR[SRW] should be read to determine the
direction of the subsequent transfer and I2CCR[MTX] should be programmed accordingly. For
slave-mode data cycles (MAAS is cleared), I2CSR[SRW] is not valid and I2CCR[MTX] must be read to
determine the direction of the current transfer. See
for more details.
11-22
2
2
2
C Interfaces
C interrupt handler can handle the interrupt. Note that the interrupts for I
C signals have time to settle. Thus, when polling I2CSR[MIF] (or any other I2CSR bits), software delays
4. Modify I2CCR to select master/slave mode, transmit/receive mode, and interrupt-enable or
5. Set the I2CCR[MEN] to enable the I
1. If the device is connected to a multimaster I
2. Select master mode (set I2CCR[MSTA]) to transmit serial data and select transmit mode (set
3. Write the slave address being called into I2CDR. The data written to I2CDR[0–6] comprises the
2
1. Clear I2CSR[MIF]
2. Read the contents of the I
C interrupt is generated (provided interrupt reporting is enabled with I2CCR[MIEN] =1) so that the
disable.
whether the serial bus is free (I2CSR[MBB] = 0) before switching to master mode.
I2CCR[MTX]) for the address cycle.
slave calling address. I2CCR[MTX] indicates the direction of transfer (transmit/receive) required
from the slave.
mode. Note that this causes I2CSR[MCF] to be cleared. See
Routine Flowchart.”
Generation of START
Post-Transfer Software Response
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C data register (I2CDR) in receive mode or write to I2CDR in transmit
2
C signals sufficient time to settle.
2
C interrupt bit (I2CSR[MIF]) is cleared. If MIF is set at any time,
2
2
C controller.
C interface.
2
C interrupt bit (I2CSR[MIF]) is also set and an interrupt
Section 11.5.8, “Interrupt Service Routine Flowchart,”
2
C system, test the state of I2CSR[MBB] to check
Section 11.5.8, “Interrupt Service
2
C1 and I
Section 11.5.8, “Interrupt
2
C2 are combined into
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